Technical data

Using the STATus System 27
Agilent N8201A Performance Downconverter Synthetic Instrument Module, 250 kHz to 26.5 GHz 541
Using the Status Registers
The Section “N8201A Core Status Register System (Page 2 of 2)" on page 547 shows
the N8201A instrument status registers and their hierarchy.
“What Status Registers Are” on page 541
“How to Use the Status Registers” on page 542
“Using a Status Register” on page 544
“Using the Service Request (SRQ) Method” on page 544
“N8201A Core Status Register System (Page 2 of 2)” on page 547
“Standard Event Status Register” on page 551
“Operation and Questionable Status Registers” on page 553
What Status Registers Are
The status system is comprised of multiple registers that are arranged in a hierarchical
order. The lower-level status registers propagate their data to the higher-level registers in
the data structures by means of summary bits. The status byte register is at the top of the
hierarchy and contains general status information for the instrument’s events and
conditions. All other individual registers are used to determine the specific events or
conditions.
The operation and questionable status registers are sets of registers that monitor the
overall instrument condition. They are accessed with the STATus:OPERation and
STATus:QUEStionable commands in the STATus command subsystem. Each register set is
made up of five registers:
Condition Register reports the real-time state of the signals monitored by this register
set. There is no latching or buffering for a condition register.
Positive Transition Register this filter register controls which signals will set a bit in the
event register when the signal makes a low to high transition (when the condition bit
changes from 0 to 1).
Negative Transition Register this filter register controls which signals will set a bit in
the event register when the signal makes a high to low transition (when the condition bit
changes from 1 to 0).
Event Register latches any signal state changes, in the way specified by the filter
registers. Bits in the event register are never cleared by signal state changes. Event
registers are cleared when read. They are also cleared by *CLS and by presetting the
instrument.