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Application Block Diagrams for 10 Gb/s

BERT Test Systems

Application Note

1. Pattern generator for use with oscilloscope

2. BER tester for use with a simple electrical DUT for 10 Gb/s

applications

3. BER tester with an external 1/16th rate clock for 10 Gb/s

applications

4. BER tester with an external divider for low-rate applications

5. BER tester with an external full-rate clock for 0.5 to 12G

applications

6. BER tester with jitter injection for stressed eye testing

7. BER tester with Agilent N4982A clock recovery unit BER testing

>12.5 Gb/s

Agilent designs and manufactures a collection of low-cost instruments and

test accessories, including a 10 Gb/s BERT for 0.5 to 12.5 Gb/s applications.

The N4962A serial BERT 12.5 Gb/s can be used for a collection of signal

integrity applications as listed below.

Each application is discussed in detail with block diagrams in this document.

For more information, please contact www.agilent.com/find/contactus

LF TrigO

HF TrigO

JitterI

EXT CKI

TX CKO

~IN

~OUT

OUT

RX CKI

RX CKO

TX CKI

N4962A serial BERT

12.5 Gb/s

DUT

Summary of content (12 pages)

PAGE 1
Agilent Application Block Diagrams for 10 Gb/s BERT Test Systems Application Note Agilent designs and manufactures a collection of low-cost instruments and test accessories, including a 10 Gb/s BERT for 0.5 to 12.5 Gb/s applications. The N4962A serial BERT 12.5 Gb/s can be used for a collection of signal integrity applications as listed below. Each application is discussed in detail with block diagrams in this document. For more information, please contact www.agilent.com/find/contactus 1.
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Pattern Generator for Use with Oscilloscope The N4962A serial BERT 12.5 Gb/s can be used as a high-performance GPIBprogrammable PRBS (pseudo-random bit sequence) generator. This application is ideally suited for measuring the eye performance of the DUT, including ‘eye mask’ measurements. A simple PRBS generator block diagram is shown in Figure 1; this setup is used to characterize the output performance of the BERT. The two small coaxial loops are shown connecting the BERT clock outputs to the clock inputs.
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In this case, we are using the ‘precision timebase’, a high-precision trigger input on the oscilloscope. This scope input can accept a higher frequency rate trigger signal, and is connected to HF TrigO (a full-rate clock) on the BERT. Even though we are using a more precise method of triggering the oscilloscope, the performance of the DUT is slowing down the transition times and increasing RMS jitter. The scope is shown making an ‘eye-mask’ measurement.
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BER Tester with an External 1/16th Rate Clock for 10 Gb/s Applications The N4962A serial BERT 12.5 Gb/s can also be synchronized to an external 1/16th rate clock for BER measurements from 9.85 to 11.35 Gb/s. This application is ideally suited for synchronizing the BERT with the system clock of a DUT, like a transceiver, SERDES, or CDR. A block diagram is shown in Figure 5. The external low-frequency (LF, clock/16) signal is connected to ExtCKI.
PAGE 5
BER tester with an External Divider for Low-Rate Applications The N4962A serial BERT 12.5 Gb/s can also be used for applications below the internal clock range of 9.85 to 11.35 Gb/s, within the operating limits of 0.5 to 12.5 Gb/s. This is accomplished by using an external divider (Agilent offers several programmable units) in the clock path, as illustrated in Figure 6. N4962A serial BERT 12.5 Gb/s ÷N ÷N TX CKI RX CKI RX CKO OUT ~OUT TX CKO EXT CKI JitterI HF TrigO LF TrigO DUT IN ~IN Figure 6.
PAGE 6
BER Tester with an External Full-Rate Clock for 0.5 to 12.5 Gb/s Applications The N4962A serial BERT 12.5 Gb/s can also be used for applications within a full range of operating rates from 500 Mb/s to 12.5 Gb/s. This is accomplished by applying an external clock signal to the BERT clock inputs, RX CKI and TX CKI, as illustrated in Figure 7. N4962A serial BERT 12.
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BER Tester with Jitter Injection for Stressed Eye Testing The N4962A serial BERT 12.5 Gb/s also has the capability to inject jitter onto the output PRBS datastream; an important component of IEEE-specified stressed eye tests. This is accomplished by applying an external signal to the JitterI input port as illustrated in Figure 8. Oscilloscope N4962A serial BERT 12.
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BER Tester with Agilent N4982A Clock Recovery Unit The N4962A serial BERT 12.5 Gb/s can also be used with a broadband clock recovery unit, like the low-cost Agilent N4982A clock recovery unit. This “AnyRate” CRU will recover a clock from a PRBS bit stream from 622 Mb/s to 13.5 Gb/s—perfect for use with the wide operating range of the Agilent BERT.
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N4962A serial BERT 12.5 Gb/s TX CKI RX CKI RX CKO DUT with PMD OUT ~OUT E/O O/E TX CKO EXT CKI JitterI HF TrigO LF TrigO IN Data input ~IN CLK output ~CLK output N4982A CRU Figure 10. Block diagram – Differential BER measurement with Agilent CRU The N4982A clock recovery unit will automatically scan between 622 Mb/s and 13.5 Gb/s, and will lock onto the highest-power frequency rate it can find. The recovered clock is ideally suited to drive the BERT error detector.
PAGE 10
BER testing >12.5 Gb/s The N4962A serial BERT 12.5 Gb/s can be used for testing > 12.5 Gb/s. The pattern generator section is capable of operating up to 15 Gb/s, but the error detector section does not operate above 12.5 Gb/s. However BER measurements can be made above 12.5 Gb/s by using a 1:2 DeMux (N4968A clock and data demultiplexer 44 Gb/s) before the error detector input and checking both de-multiplexed data signals independently. In the example below the N4962A serial BERT 12.
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Setup Instructions 1. Use an external RF signal generator and a 6 dB power splitter to send the clock signal to both the N4962A serial BERT 12.5 GB/Sand the N4968A clock and data demultiplexer 44 Gb/s. 2. Bypass the N4962A serial BERT 12.5 Gb/s internal clock path, and connect the clock signal directly to the pattern generator section clock input TX CKI. A level of +4 dBm at TX CKI should be sufficient.
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