Technical data

Table 7
Source Mode Description
Blanking Alternate The signal at Aux In
controls whether output is
generated:
If Aux In=logic high,
output is generated.
If Aux In=logic low, no
output is generated.
The generated output
depends on the Select
command (A Half, B half,
AB Half).
How the Serial BERT Sends Triggers
The Serial BERT can repeatedly send trigger signals either according to a clock
divider, or according to the output pattern.
The trigger pulse is sent from the pattern generator's Trigger/Ref Clock Out port.
If the trigger mode is Divided Clock, the trigger is sent according to the clock ratio.
N O T E
If the Divider Factor n is uneven (e.g. 3), the clock's duty cycle will not be 50%, but
the signal will stay high for (n+1)/2 and low for (n-1)/2. This results in a DCD of 0.5
UI.
If the trigger mode is Pattern, the trigger is sent according to the selected pattern.
Depending on the selected pattern, you have the following possibilities for setting
the position of the trigger:
• PRBS and PRBN patterns
You can define the pattern, the occurrence of which sends the trigger.
• Mark Density and Zero Substitution patterns
You can define the bit position that causes a trigger to be sent.
• User patterns
You can define whether a trigger is sent every time a pattern is sent, or every
time a pattern is changed (for alternate patterns).
3 Recommended Programming Techniques
58 Agilent J-BERT N4903B High-Performance Serial BERT
Triggering upon Divided Clock
Triggering upon Pattern