Technical data

Table 5
Bit Mnemonic Description
0 DATA LOSS This bit is set when the
data source is turned off,
not connected, or the
cables or device is faulty.
This bit can also set when
the 0/1 threshold is not in
the eye limits of the
incoming data signal. In
this last case, use Auto
Align or select Avg 0/1
Threshold.
1-4 Not used
5 CLOCK LOSS This bit is set when the
pattern generator receives
no external clock signal or
the error detector receives
no clock input signal. To
find out which of the 2
events is causing this bit to
set, you must poll the
Clock Loss Status
Register; see “Clock Loss
Register” on page 30.
6 PROTECT ED DATA IN This bit indicates that the
protection mechanism for
the Data Input port of the
error detector was
activated, e.g. the voltage
or current measured at this
port was out of range.
7 PROTECT PG DELAY CTRL
IN
This bit indicates that the
protection mechanism for
the Delay Control Input
port of the pattern
generator was activated,
e.g. the voltage or current
measured at this port was
out of range.
3 Recommended Programming Techniques
32 Agilent J-BERT N4903B High-Performance Serial BERT