Technical data

This is the clock signal at the 10 MHz Ref In port. A frequency of 10 MHz is
required.
• EXTPLL
Selects the clock signal at the CLK IN port. It is routed internally through a PLL.
The frequency is automatically measured and used.
• EXTPLLMAN
In this variant of EXTPLL, you can measure the frequency of the external source
clock (see “SENSe6:FREQuency[:CW|:FIXed]?” on page 193) and set the clock
frequency explicitly (see “SOURce9:FREQuency[:CW|FIXed][?] ” on page 162).
SENSe6:EXTernal:DIVider[?]
IAgilentN490xPGClockIn.ExternalDivider
SENSe6:EXTernal:DIVider
SENSe6:EXTernal:DIVider[?]
<NR1>
<NR1>
You can have sinusoidal jitter and spread spectrum clocking simultaneously by
using an external SSC modulated clock signal applied to the Ext Input of the
generator. The clock signal at the Ext Input has to be in the range from 6.75 Gb/s
up to 12.5 Gb/s. This SCPI command can be used to specify a divider so as to
generate data rate below 6.75 Gb/s at the Data Output.
SENSe6:EXTernal:PLLoop:DIVider[?]
IAgilentN490xPGClockIn.ExternalDividerMultiplierPLL
:SENSe6:EXTernal:PLLoop:DIVider[?]
:SENSe6:EXT:PLL:DIV[?]
<NR1>
<NR1>
5 SCPI Command Reference
194 Agilent J-BERT N4903B High-Performance Serial BERT
IVI-COM Equivalent
Syntax
Input Parameters
Return Range
Description
IVI-COM Equivalent
Syntax
Input Parameters
Return Range