Technical data

Table 38
Name Description under
:VOLTage[:LEVEL][:IMMediate]:HIGH[?] “SOURce5:VOLTage[:LEVel]
[:IMMediate]:HIGH[?] ” on page 187
:VOLTage[:LEVEL][:IMMediate]:LOW[?] “SOURce5:VOLTage[:LEVel]
[:IMMediate]:LOW[?] ” on page 187
:VOLTage[:LEVEL][:IMMediate]:OFFSet
[?]
“SOURce5:VOLTage[:LEVel]
[:IMMediate]:OFFSet[?] ” on page 187
:VOLTage[:LEVEL]:LLEVel[?] “SOURce5:VOLTage:LLEVel[?] ” on page
188
:VOLTage:PROTection:RESet[?] “SOURce5:VOLTage:PROTection:RESet
[?] ” on page 188
:VOLTage:PROTection[:STATe][?] “SOURce5:VOLTage:PROTection
[:STATe][?] ” on page 189
SOURce5:DIVider[?]
IAgilentN490xPGClock2.SubRateDivider
SOURce5:DIVider <NR1>
SOURce5:DIVider?
This command is used to set the clockrate divider. The range is 2 to 128.
The query returns the current divider setting.
N O T E
The subrate clock has a fixed amplitude and no fixed phase correlation with the
actual clock.
N O T E
If the Divider Factor n is uneven (e.g. 3), the clock's duty cycle will not be 50%, but
the signal will stay high for (n+1)/2 and low for (n-1)/2. This results in a DCD of 0.5
UI.
SCPI Command Reference 5
Agilent J-BERT N4903B High-Performance Serial BERT 185
IVI-COM Equivalent
Syntax
Description