Keysigth Technologies N4903B J-BERT

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06 | Keysight | J-BERT N4903B High-Performance Serial BERT, 7 Gb/s and 12.5 Gb/s - Data Sheet
Jitter Tolerance Tests
alibrated and integrated jitter injection
– Periodic jitter single and dual-tone ption J10
– Sinusoidal jitter ption J10
– Random jitter and spectrally distributed RJ ption J10
– Bounded uncorrelated jitter ption J10
– Intersymbol interference ISI ption J20
– Sinusoidal interference ption J20
– Spread spectrum clocing SS and residual SS ption
J11)
External jitter injection
sing an external source connected to delay control input.
ser controls
Manual jitter composition
ption J10 PJ 1 / 2 SJ RJ sRJ and BJ
ption J20 ISI and sinusoidal interference
ption J11 SS and residual SS
This screen allows the user to set up combinations of jitter types
and jitter magnitudes easily. Therefore a calibrated stressed eye
with more than 50 eye closure can be set up for receiver
testing. Additional jitter can be injected with the interference
channel. It adds ISI and differential/single mode sinusoidal
interference.
Automated jitter tolerance characterization
ption J10
This test automatically sweeps over SJ freuency based on the
selected start/stop freuency steps accuracy BER level
condence level and DT relax time. The green dots indicate
where the receiver tolerated the injected jitter. The red dots show
where the BER level was exceeded. By selecting a tested point
the jitter setup condition is restored for further analysis. The
compliance curve can be shown on the result screen for
immediate result interpretation. This automated characterization
capability saves signicant programming time.
Automated jitter tolerance compliance
ption J12
This test automatically veries compliance against a receivers
jitter tolerance curve limits specied by a standard or by the user.
Most of the popular serial bus standards dene jitter tolerance
curves. This option includes a library of jitter tolerance curves for
SATA ibre hannel B-DIMM 10 GbE/XAI EI 6/11 G and
XP/XI. Pass/fail is shown on a graphical result screen which
can be saved and printed. A comprehensive compliance report
including the jitter setup and total jitter results for each test
point can be generated and saved as a html le for simple jitter
tolerance test documentation.
igure 3. Manual jitter composition. This allows a combination of jitter types to be
injected. Example shows a typical jitter setup for a PIe 2.0 add-in card test
igure 4. Automated jitter tolerance characterization. The green circles show
where DT wors within the reuired BER-level
igure 5. Result screen of the automated jitter tolerance compliance. A library of
jitter tolerance curves is available