Keysigth Technologies N4903B J-BERT
dataTec ▪ Ferdinand-Lassalle-Str. 52 ▪ 72770 Reutlingen ▪ Tel. 07121 / 51 50 50 ▪ Fax 07121 / 51 50 10 ▪ info@datatec.de ▪ www.datatec.de
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04 | Keysight | J-BERT N4903B High-Performance Serial BERT, 7 Gb/s and 12.5 Gb/s - Data Sheet
The J-BERT N4903B high-performance serial BERT provides the
most complete jitter tolerance test for embedded and forwarded
cloc devices.
It is the ideal choice for R&D and validation teams characterizing
and stressing chips and transceiver modules that have serial I/
ports up to 7 Gb/s 12.5 Gb/s or even 14.2 Gb/s. It can
characterize a receivers jitter tolerance and is designed to prove
compliance to todays most popular serial bus standards such as
– PI Express
– SATA/SAS
– DisplayPort
– SB Super Speed
– MIPI M-P
– SD S-II
– Thunderbolt
– ibre hannel
– PI
– Memory buses such as fully buffered DIMM2
– Bacplanes such as EI IEEE Inniband
– 10 GbE/ XAI
– XP/XI SP
– 100 GbE 10x 10G or 4x 25G
Touch screen control of all J-BERT parameters
Remote operation via AN GPIB SB2 or GI
control via built-in web server
Press the Jitter button to set all
jitter parameters you need
Accurate characterization is achieved with clean signals from the
pattern generator which features exceptionally low jitter and
extremely fast transition times. Built-in and calibrated jitter
sources allow accurate jitter tolerance testing of receivers.
Test set-up is simplied signicantly because the J-BERT
N4903B is designed to match serial bus standards optimally.
It offers differential I/s variable voltage levels on all signal
outputs built-in jitter and ISI pattern seuencer reference cloc
outputs tunable DR pattern capture and bit recovery mode to
analyze cloc-less and non-deterministic patterns.
aster test execution is possible with J-BERTs automated jitter
tolerance tests and fast total jitter measurements.
J-BERT N4903B High-Performance Serial BERT
igure 2. J-BERT N4903B The most complete jitter tolerance test solution for
testing embedded and forwarded cloc devices