Keysigth Technologies N4903B J-BERT

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20 | Keysight | J-BERT N4903B High-Performance Serial BERT, 7 Gb/s and 12.5 Gb/s - Data Sheet
Error Detector Specications continued
J-BERT measurements
BER results
Symbol error ratio SER and calculated BER ption A02
rame error rate ER analysis ption A02
BER results with ltering of 8b/10b coded ller symbols or
128b/130b coded SPS symbols ption A02
Accumulated BER results
Accumulated errored s and 1s
G.821
Error-free intervals
Accumulated parameters
Burst results
Eye diagram results
1-/0- level
Eye height/amplitude/width
Jitter p-p and rms
ross-over voltage
Signal to noise ratio
Duty cycle distortion
Extinction ratio
Measurement suite
BERT scan with RJ/DJ separation
Spectral jitter decomposition
Eye contour
uic eye diagram and BER contour
ast eye mas
utput level and  factor
Error location capture
ast total jitter
Pattern capture
Trigger output TRIG T
Pattern trigger mode
This provides a trigger synchronized with the selected error
detector reference pattern. In pattern mode the pulse is synchro-
nized to repetitions of the output pattern. It generates 1 pulse for
every 4th PRBS pattern.
Divided cloc mode
In divided cloc mode the trigger is a suare wave.
Clock divider 4, 8, 16 up to 11 Gb/s
32, 40, 64, 128 up to 12.5 Gb/s
Levels High: +0.5 V typical
Low: - 0.5 V typical
Minimum pulse width Pattern length x clock period/2
e.g. 10 Gb/s with 1000 bits = 50 ns
Interface DC coupled, 50 Ω noinal
Connector SMA female
Table 25. Specications for trigger output
Error output ERR T
This provides a signal to indicate received errors. The output is
the logical R of errors in a 128 bit segment of the data.
Interface format RZ, active high
Levels High: 1 V typical
Low: 0 V typical
Pulse width 128 clock periods
Interface DC coupled, 50 Ω noinal
Connector SMA female
Table 26. Specications for error output