Keysigth Technologies N4903B J-BERT

dataTec ▪ Ferdinand-Lassalle-Str. 52 ▪ 72770 Reutlingen ▪ Tel. 07121 / 51 50 50 ▪ Fax 07121 / 51 50 10 ▪ [e-mail] ▪ www.datatec.de
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18  eysight  J-BERT N4903B igh-Performance Serial BERT 7 Gb/s and 12.5 Gb/s - Data Sheet
Error Detector Specications
Error detector ey characteristics
– True differential inputs to match todays ports
– Built-in DR with tunable loop-bandwidth up to 12 Mz
– Auto-alignment of sampling point
– Bit recovery mode for unnown data trafc ption A1
– SER/ER analysis of coded and retimed data ption A02
– Burst mode for testing recirculating loop
– BER result and measurement suite
– uic eye diagram and mas with BER contours
Data inputs DATA IN
Range of operation 150 Mb/s to 12.5 Gb/s (Option C13)
150 Mb/s to 7 Gb/s (Option C07)
Format NRZ
Max. input amplitude 2.0 V
Termination voltage
1
-2 V to +3 V or off
true differential mode
Sensitivity
2
< 50 mV pp
Intrinsic transition time
3
25 ps typical 20% to 80%, single ended
Decision threshold range -2 V to +3 V in 1 mV steps
Maximum levels -2.2 V to +3.2 V
Phase margin
4
1 UI – 12 ps typical
Clock-to-data
sampling delay
± 0.75 ns in 100 fs steps
Interface Single-ended: 50 Ω nominal,
differential: 100 Ω nominal
Connector 2.4 mm female
1. loc/data sampling delay range selectable 2  operating voltage win-
dow, which is in the range between
-2.0  to 3.0 . The data signals termination voltage and decision
threshold have to be within this voltage window.
2. At 10 Gb/s BER 10
-12
, PRBS 2
31
-1. or input levels  100 m manual
threshold value adjustments may be reuired.
3. At cable input at E levels.
4. Based on the internal cloc.
loc inputs  IN
The error detector reuires an external cloc signal to sample
data or it can recover the cloc from the data signal using the
built-in cloc data recovery DR.
Frequency range 150 MHz to 12.5 GHz (Option C13);
150 MHz to 7 GHz (Option C07)
Amplitude 100 mV to 1.2 V
Sampling Positive or negative clock edge
Interface C coupled, 50 Ω noinal
Connector SMA female
Figure 25. Front panel connectors for error detection
Table 21. Specication for the cloc input
loc data recovery
The error detector can recover the cloc from the incoming data
stream with the built-in cloc data recovery DR. The recovered
cloc signal is available at the aux output.
Input data rate 1 Gb/s to 12.5 Gb/s
1
(Option C13)
1 Gb/s to 7 Gb/s (Option C07)
CDR clock output jitter 0.01 UI rms (RJ) typical
2
Interface C coupled, 50 Ω noinal
Connector SMA female
1. ith bit recovery mode ption A01 enabled the max data rate is 11.5
Gb/s. hen using SER/ER analysis ption A02 the max. data rate is
11.5 Gb/s. ver-programming up to 12.5 Gb/s is possible but SER/ER
results are not guaranteed.
2. hen measured with PRBS 2
23
-1
Table 20. Specications for error detector
Table 22. Specications for the cloc data recovery ptions 07
13