Keysigth Technologies N4903B J-BERT

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12 | Keysight | J-BERT N4903B High-Performance Serial BERT, 7 Gb/s and 12.5 Gb/s - Data Sheet
AX input AX IN
hen the alternate pattern mode is activated the memory is split
into two parts and the user can dene a pattern for each part.
Depending on the operating mode of the auxiliary input the user
can switch the active pattern in real time by applying a pulse
mode 1 or a logical state mode 2 to the auxiliary input. If the
alternate pattern mode is not activated the user can suppress
the data on the data output by applying a logical high to the
auxiliary input mode 3.
Levels TTL compatible
Interface DC coupled, 50 Ω noinal
Connector SMA female
10 Mz reference output 10 M RE T
The external error add input adds a single error to the data output
for each rising edge at the input. hen electrical idle is selected
for the data and aux data outputs a logical high state causes
the output to transition to electrical idle state. A logic low state
causes the outputs to return to normal operation.
Amplitude   into 50 Ω tpical
Interface AC coupled,
50 Ω output ipedance
Connector BNC, rear panel
Table 7. Specications for the 10 Mz reference output
Table 9. Specications for auxilliary input
Auxillary cloc output AX  T
This output is intended as cloc input for N4916B de-emphasis
signal converter and the 28 Gb/s 21 multiplexer N4876A.
Output level > 150 mV typical
Clock signal Full-rate
Interface C coupled, 50 Ω noinal
Connector SMA female
Table 10. Specications for auxillary cloc output
Trigger/reference cloc outputs
TRIGGER/ RE  T
This output provides a trigger signal synchronous with the
pattern for use with an oscilloscope or other test euipment.
Typically there is a delay of 32 ns between trigger and data
output for data rates  620 Mb/s. The trigger output has two
modes.
Pattern trigger mode or PRBS patterns the pulse is
synchronized with a user specied trigger pattern. ne pulse is
generated for every 4th PRBS pattern.
Divided cloc mode Generates a suare wave cloc with the
freuency of the full-rate cloc divided by 2 4 8 10 16 20 24
25 26 up to 32792. It is possible to enable/disable SJ SS or
residual SS for this output to use it as a lower freuency
reference cloc.
Pattern Generator Specications
(continued)
Error add input ERRR ADD
The external error add input adds a single error to the data output
for each rising edge at the input. hen electrical idle is selected
for the data and aux data outputs a logical high state causes
the output to transition to electrical idle state. A logic low state
causes the outputs to return to normal operation.
Levels TTL compatible
Interface DC coupled, 50 Ω noinal
Connector SMA female
Table 6. Specications for error inject input
Pulse width Square wave
Amplitude/ resolution 0.050 V to 1.800 V, 5 mV steps.
Addresses LVDS, CML, PECL, ECL
(terminated to 1.3V/0 V/-2 V),
low voltage CMOS
Output voltage window - 2.0 V to +3.0 V
redened leels ECL, PECL (3.3V), LVDS, CML
Transition times < 20 ps typical (20% to 80%)
< 25 ps typical (10% to 90%)
Interface
1
DC coupled, 50 Ω noinal,
Single ended or differential
Connector 2.4 mm female
1. nused output must be terminated with 50 to GND.
Table 8. Specications for trigger/reference cloc output