Specifications
Chapter 7: Theory of Operation
Backplane Assembly
129
Figure 7-7 10 GHz clock generation
The external 10 MHz reference is applied through a rear- panel BNC connector and runs
to the backplane assembly. Users can select between an internal and external reference
through a dialog box in the oscilloscope application. A detector circuit consisting of a
detector diode and a non- inverting op- amp gain stage followed by a window comparator
ensures the user supplies a 10 MHz signal of the correct amplitude (- 5 dBm minimum
to +10 dBm maximum). The detector circuit produces a warning if the external reference
input signal is too small or too large, but not if the signal is within the specified
operating range. The frequency of this external reference must be very close to 10 MHz
(typically +- 20 ppm) or the 100 MHz oscillator will not be able to lock to it.
The internal and external reference inputs are applied to each input of a very high
isolation RF switch. The isolation between the two inputs is greater than 100 dB to
prevent the internal and external 10 MHz clocks from interfering with each other. This
10 MHz reference, either internal or external, is split into two signal paths. One path
goes to the rear panel as described earlier for use as a reference for some other
instrument, and the second path is limited and filtered for use as the reference input
to the 100 MHz phase- locked oscillator. The signal that goes to the rear panel is very
close to the same amplitude as either the internal reference oscillator output amplitude
or the input amplitude of the external signal applied to the external reference input
connector, depending on which one the user selected. The reference signal that goes to
the 100 MHz oscillator input is a sine wave of amplitude 0 dBm +/- 3 dB.
The actual 10 GHz sample clock is generated with a DRO that is phase- locked to the
100 MHz oscillator output.
Trigger System
The trigger system contains an FPGA that is used to coordinate the trigger system
operation and two trigger ICs. The FPGA uses a 212.5 MHz clock that is synchronous
to the main communication FPGA clock. The trigger ICs are the main trigger- handling
chips, programmed with a serial interface from the main communication FPGA. Each
trigger IC also receives two DAC signals that set the internal clock and data timers.
The trigger IC is used for setting the timing for the logic trigger from 0.3 ns to 20 ns.
The trigger FPGA is used for times greater than 20 ns.
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