Specifications
Chapter 7: Theory of Operation
Backplane Assembly
127
The main FPGA uses three identical buses to communicate with three different
downstream FPGAs. The buses are 8- bit parallel buses with miscellaneous control
signals. One bus is used to control the trigger functions in the backplane board and
one bus connects to each of the two acquisition boards. A separate bus for each FPGA
minimizes timing problems and reflections. The FPGAs on the acquisition assemblies
are used to control the oscilloscope functions on each of those assemblies. On power-
up, after the PC software recognizes the two acquisition assemblies, it loads the trigger
FPGA and the acquisition FPGAs using these buses. When programming is complete,
the PC communicates with the downstream FPGA over the same buses.
The main FPGA provides access to the memory controllers over a separate bus to each
acquisition board. The acquired data is retrieved from the acquisition boards over these
buses.
Timebase System
The oscilloscope timebase system generates and distributes all of the clock signals that
control or are synchronized to waveform acquisition. Figure 7- 6 shows the timebase
system including its circuitry.
Figure 7-6 Time base
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