Specifications

Chapter 7: Theory of Operation
Backplane Assembly
126
Main FPGA
The main FPGA (field- programmable gate array) is the only communication link from
the oscilloscope hardware to the PC system. All system controls and data pass through
the main FPGA. Figure 7- 5 shows the connections to the main FPGA.
Figure 7-5 Main communication FPGA connections
During a successful power- up, a PROM configures the FPGA over an 8- bit bus. The
PROM comes pre- loaded with the required bits, but can be re- programmed through its
JTAG port with software or through a Xilinx programming cable plugged into a normally
no- loaded connector.
Once the FPGA is configured, the FPGA controls the power sequencing system, which
allows the rest of the system to power up and become fully functional. When everything
is ready the FPGA sends a reset to the PC motherboard so that Windows and the
oscilloscope software can start up.
The FPGA is a device on the PCIe bus (x1) interfaced with an external Philips PHY.
The PHY drives the PCIe signals out two SATA connectors. Two SATA cables are
required to connect the backplane board to the motherboard. Because running PCIe
over SATA cables is not a standard usage, a special motherboard is required that has
an x1 port wired into two SATA connectors. When Windows is booted up, the main
communication FPGA must show up in the device listing (as Infiniium Acquisition) for
the oscilloscope application to run and control the oscilloscope hardware.
The main FPGA contains several registers that can be used to control peripherals and
fan speed, configure and communicate with other FPGAs, and pass sampled data to
the PC for reconstruction of the measured waveform on the oscilloscope display. In
addition, the FPGA generates PCI interrupts for all oscilloscope- related special events
such as a front- end overload, the timer done, or a stopped cooling fan.
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