Specifications

Chapter 7: Theory of Operation
Backplane Assembly
128
The fundamental sample clock is a single- ended 10 GHz signal created by the timebase
generation system. Multiple copies of this clock are created there and distributed to
each Oak module and the timebase IC through semi- rigid coax cables. In each case, the
single- ended signal is converted to a differential signal using a bandpass filtered 180°
phase splitter implemented using microwave structures on shielded inner layers of the
PCB. The clock distribution system divides this clock and distributes phase- aligned
lower speed clocks to the acquisition boards.
The timebase IC divides the 10 GHz CW clock down into multiple 1 GHz and 250 MHz
clocks. The 1 GHz DigClk clocks are gated by DigRun so that the ADCs can be
synchronized with each other. The timebase IC also performs some of the time
interpolator functionality by synchronizing the system trigger to the 1 GHz DigClk and
generating the first two MSBs of the trigger interpolation value.
The 10 GHz SampClk 10G signal is divided down to 1 GHz for use as TbClk and DigClk.
TbClk is divided by four to generate RefClk, which drives the memory controllers and
the calibrator chip. These four 250 MHz outputs are phased in quadrature to minimize
the coupling of sub- harmonics into the DigClk signals. The RefClk signal that goes to
the calibrator chip must be disabled when not in use by the calibrator system.
SysTrig is the primary output from the trigger system. It is synchronous to the trigger
event and asynchronous to the time base clock, TbClk. The timebase IC synchronizes
SysTrig to the time base clock with low probability of metastability, producing the
TbTrig signal. TbTrig pulses high once immediately after every rising edge of SysTrig.
The timebase IC also produces a trigger signal that is synchronous to RefClk. This
signal, RefTrig, pulses high once immediately after every rising edge of SysTrig. RefTrig
tells the memory controller when a trigger event has occurred. It is important to note
that although DigRun and RefTrig are both synchronous to RefClk, their phase
relationship to RefClk s not important. As long as their phase relationship is consistent,
the memory controller can adjust for it. Finally, the timebase IC records the phase
relationship between RefTrig and TbTrig, and provides it as the 2- bit digital value, Nosc.
Nosc[0] is driven by the 500 MHz clock and Nosc[1] is driven by the 250 MHz clock.
The clock distribution system also creates and distributes clocks for other purposes. A
212.5 MHz oscillator creates a clock that is intentionally not an integer division of the
sample clock. This approach prevents beat frequency effects from showing up in the
captured data. The clock is sent to the trigger FPGA and to the main FPGA.
The trigger FPGA uses the clock for capturing and processing trigger signals. The FPGA
propagates a copy of this clock to each trigger ASIC.
The main FPGA uses the clock to generate the bus clocks for communications with the
other FPGAs and the memory controller ICs. It sends a 62.5 MHz clock as part of the
FPGA bus to each FPGA. It generates another clock for the memory controller buses.
This clock is buffered and fanned out in the clock distribution system, then driven to
the memory controller ICs and back to the main FPGA.
Trigger System
The trigger system contains an FPGA that is used to coordinate the trigger system
operation and two trigger ICs. The FPGA uses a 212.5 MHz clock that is synchronous
to the main communication FPGA clock. On power- up it is blank and is loaded from
the Infiniium oscilloscope driver.
The trigger ICs are the main trigger- handling chips, programmed with a serial interface
from the main FPGA. Each trigger IC also receives two DAC signals that set the internal
clock and data timers. The trigger IC is used for setting the timing for the logic trigger
from 0.3 ns to 20 ns. The trigger FPGA is used for times greater than 20 ns.