Specifications

4-9
Operating Features and Specifications
Subrate Clock & Data (inverted) Outputs
Subrate Clock & Data (inverted) Outputs
Four subrate Data outputs (parallel data out ports) and one subrate Clock output are
available. Subrate Data and Clock are at 1/4 the main Data and Clock rate. Subrate data is
inverted relative to the main data output. When the main data is a pure PRBS, the subrate
data is a PRBS at 1/4 the main data rate (every 4th bit is output). When a RAM based
pattern (including mark density and zerosub patterns) is selected the data pattern output
from each subrate port depends on the pattern length and will change if the trigger bit
position changes. Refer to Appendix B for additional information.
The following subrate features are provided:
Features
• Data high-level adjust.
• Data amplitude adjust.
• Clock high-level adjust.
• Clock amplitude adjust.
• Set Clock and Data to ECL.
• Set external termination voltage 0/−2V or ac coupled.
Specifications
Frequency range: 1/4ofmainclockrate.
Interface: dc coupled, 50Ω, reverse terminated.
Amplitude: 0.5 V to 1 V pp in 10 mV steps.
Range: 0to−1.5 V in 10 mV steps.
Connector: SMA female connector.
Trigger Output
Provides an electrical trigger synchronous with the pattern for use with an oscilloscope or
other test equipment. It operates in two modes, pattern and divided clock. Refer to pages
7-16 and 7-17 for more information on Trigger Outputs.
Features
• Pattern or clock trigger
• Pattern trigger position set