Specifications

3-5

Interrogating the Instrument Status

Status Byte Register Group

The Status Byte is the summary register to which the other registers report. Each reporting

FAIL Summary Bit 0, indicates there are bits set in the Failure Status register. This

Bit in turn indicates there has been a major hardware failure in the

instrument.

QUES Summary Bit 3, indicates that a bit has been set in the Questionable Data

Bit Status register. The bits in the Questionable Data Status register

indicate when a signal is of questionable quality.

MAV Summary Bit 4, is the message available summary bit. This bit remains set

Bit until all the output messages are read from the instrument. The

instrument stores its messages in an output queue. These messages

are read by addressing the instrument to talk and reading the data.

The availability of this data is summarized by the MAV bit.

ESB Summary Bit Bit 5, indicates that a bit in the Standard Event register has been set.

RQS or MSS Bit 6 of the Status Register has two definitions depending of the

Summary bit method used to access the register. If the value of the register is read

using the serial poll bit 6 is referred to as the RQS (request service

bit) as this is the means used to inform the active controller that the

instrument has set the service request control line (SRQ) i.e.

interrupted the controller.

If the register is read using the *STB? common query command,

then bit 6 is referred to as the master summary bit or MSS bit. It is

this bit which indicates the instrument has requested service. The

Table 3-1 Status Byte Register

Bit # Mnemonic Description Bit Value

0 FAIL Failure Status register summary bit. 1

1 - This bit is not used

2 - This bit is not used.

3 QUES Questionable Data Status register summary bit. 8

4 MAV Output queue summary bit. 16

5 ESB Standard Event register summary bit. 32

6 RQS or MSS SRQ or master status summary bit. 64

7 OPER Operation Status register summary bit. 128