Specifications

2-8
Programming the HP 71612 Series
Device/Controller Synchronization Techniques
On virgin power-on, all registers and filters are disabled except: 1) the PON, CME and
EXE bits of the Standard Event Status Register and its summary bit
in the Status Byte, 2) all the assigned bits of the FAILURE register
and its summary bit in the Status Byte. In this way, a user will not
be swamped by SRQs. An SRQ will only be generated if the
instrument receives invalid commands or queries, or a major
hardware failure occurs. The transition filters will be set to allow all
conditions and events to pass.
The event registers and the error queue are cleared at each and every power-up.
Device/Controller Synchronization Techniques
Overlapped Commands
As defined within IEEE Std 488.2-1987 the following commands are overlapped:
GATe[:STATe] ON for SINGLE TIMED repetitive periods in the Error Detector.
EYE: TCENter|EYE:TCENtre ONCE|ON
EYE ACENter|EYE:ACENtre ONCE|ON
ELOCation
An example of a polled implementation of a clock to data delay alignment is included at
the rear of this manual.
An alternative method might involve the configuration of the status reporting structure to
cause an SRQ interrupt on one or both transitions of the required bit within the operational
status register.
For the overlapped commands listed above, however, a simple and convenient method for
holding off the controller until the overlapped operation has completed involves the use of
the *WAI command as shown below in the extract from a Basic Language program where
having configured a single gating period of 10 seconds the querying of the bit count result
is held off until the gating period has elapsed.
INTEGER GatePeriod
REAL BitCount
ASSIGN @Bert TO 718
GatePeriod=l0 ! seconds
OUTPUT @Bert; "SENSE 1 : GATE: MODE SING"
OUTPUT @Bert; "SENSEl : GATE : MANNER TIME"
OUTPUT @Bert;"SENSE1:GATE:PER:TIME "&VAL$(GatePeriod)
OUTPUT @Bert;"SENSE1:GATE:STATE ON" ! run gating
OUTPUT @Bert; "*WAI"
OUTPUT @Bert; "FETCH:SENSE2:BCOUNT?"
ENTER @DBert ;BitCount