Specifications

To test the single-clock, multiple-edge, state acquisition
(logic analyzer)
Testing the single-clock, multiple-edge, state acquisition verifies the performance of
the following specifications:
• Minimum master to master clock time
• Maximum state acquisition speed
• Setup/Hold time for single-clock, multiple-edge, state acquisition
• Minimum clock pulse width
This test checks two combinations of data using a multiple-edge single clock at three
selected setup/hold times.
Equipment Required
Equipment Critical Specifications Recommended
Model/Part
Pulse Generator 100 MHz 3.5 ns pulse width, < 600 ps rise time HP 8133A option 003
Digitizing Oscilloscope ≥ 6 GHz bandwidth, < 58 ps rise time HP 54750A, with HP 54751A
plugin
Adapter SMA(m)-BNC(f) HP 1250-1200
SMA Coax Cable (Qty 3) 18 GHz bandwidth HP 8120-4948
Coupler BNC(m)(m) HP 1250-0216
BNC Test Connector,
6x2 (Qty 4)
Set up the equipment
1 Turn on the equipment required and the logic analyzer. Let them warm up for
30 minutes before beginning the test if you have not already done so.
2 Set up the pulse generator according to the following table.
Pulse Generator Setup
Timebase Channel 2 Period Channel 1
Mode: Int Mode: Square Divide: Divide ÷ 2 Mode: Pulse
Period: 10.000 ns Divide: SQUARE ÷ 2 Ampl: 0.50 V Delay: 0.000 ns
Delay: 0.000 ns Offs: 0.00 V Width: 4.00 ns
High: −0.90 V High: −0.90 V
Low: −1.70 V Low: −1.70 V
COMP: Disabled
(LED Off)
COMP: Disabled
(LED Off)
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