Specifications

9 Using the Delay mode of the pulse generator channel 1, position the pulses
according to setup time of the setup/hold combination selected, +0.0 ps or −100 ps.
a
On the Oscilloscope, select [Define meas] Define ∆ Time - Stop edge: falling.
b On the oscilloscope, select [Shift] - width: channel 2, then select [Enter] to verify the
clock signal pulse width (- width (2)). If the pulse width is outside the limits, adjust the
pulse generator channel 2 width until the clock pulse width is 3.480 ns, +20 ps or -80
ps.
c
On the oscilloscope, select [Shift] ∆ Time. Select Start src: channel 1, then select
[Enter] to display the setup time (∆ Time (1)-(2)).
d Adjust the pulse generator channel 1 Delay until the pulses are aligned according the
the setup time of the setup/hold combination selected, +0.0 ps or -100 ps.
10 Select the clocks to be tested.
a Select the clock field to be tested, then select the clock edges as indicated in the table.
The first time through this test, use the top clocks and edges (HP 1660C/CS/CP and
HP 1661C/CS/CP).
Clocks
HP 1660C/CS/CP and HP 1661C/CS/CP HP 1662C/CS/CP and HP 1663C/CS/CP
J↓ + M↓ + N↓ J↓ + K↓ + L↓ + M↓
K↓ + L↓ + P↓
b Select Done to exit the Master Clock menu.
Testing Performance
To test the multiple-clock, multiple-edge, state acquisition (logic analyzer)
3–47