Specifications

d Adjust the pulse generator channel 1 Delay until the pulses are aligned according the
the setup time of the setup/hold combination selected, +0.0 ps or -100 ps.
4
Select the clocks to be tested.
a Select the clock field to be tested and then select the clock edges as indicated in the
table. The first time through this test, use the top clocks and edges (HP 1660C/CS/CP
and HP 1661C/CS/CP). Note that the clocks used depends on which logic analyzer
you have.
Clocks
HP 1660C/CS/CP and HP 1661C/CS/CP HP 1662C/CS/CP and HP 1663C/CS/CP
J↑ + M↑ + N↑ J↑ + K↑ + L↑ + M↑
K↑ + L↑ + P↑
b Connect the rising edge clocks to the pulse generator channel 2 output.
c Select Done to exit the Master Clock menu.
Testing Performance
To test the multiple-clock, multiple-edge, state acquisition (logic analyzer)
3–45