Specifications

Supplemental Characteristics (logic analyzer)
Probes
Input Resistance 100 kΩ, ± 2%
Input Capacitance ~ 8 pF
Minimum Voltage Swing 500 mV, peak-to-peak
Threshold Range ± 6.0 V, adjustable in 50-mV increments, CAT I
Maximum Input Voltage ± 40 volts, CAT I
State Analysis
State/Clock Qualifiers 1660/61C,CP,CS - 6; 1662C,CP,CS - 4; 1663C,CP,CS - 2
Time Tag Resolution
*
8 ns or 0.1%, whichever is greater
Maximum Time Count
Between States 34 seconds
Maximum State Tag Count
*
4.29 x 10
9
Timing Analysis
Sample Period Accuracy 0.01 % of sample period
Channel-to-Channel Skew 2 ns, typical
Time Interval Accuracy ± [sample period + channel-to-channel skew
+(0.01%)(time reading)]
Triggering
Sequencer Speed 125 MHz, maximum
State Sequence Levels 12
Timing Sequence Levels 10
Maximum Occurrence Counter
Value 1,048,575
Pattern Recognizers 10
Maximum Pattern Width 136 channels in HP 1660C,CP,CS, 102 channels in
HP 1661C,CP,CS, 68 channels in HP 1662C,CP,CS,
34 channels in HP 1663C,CP,CS
Range Recognizers 2
Range Width 32 bits each
Timers 2
Timer Value Range 400 ns to 500 seconds
Glitch/Edge Recognizers 2 (timing only)
Maximum Glitch/Edge Width 136 channels in HP 1660C,CP,CS, 102 channels in
HP 1661C,CP,CS, 68 channels in HP 1662C,CP,CS,
34 channels in HP 1663C,CP,CS
*
Maximum state clock rate with time or state tags on is 100 MHz. When all pods are assigned to a state or timing machine, time or
state tags halve the memory depth.
General Information
Supplemental Characteristics (logic analyzer)
1–7