Specifications

Characteristics (pattern generator)
The HP 1660CP Logic Analyzers also include the following characteristics:
Output channels 16 channels at 200 MHz clock; 32 channels at
100 MHz clock
Memory depth 258,048 vectors
Logic levels (data pods) TTL, 3-state TTL/3.3v, 3-state TTL/CMOS,
ECL terminated, ECL unterminated, and differential
ECL (without pod)
Data inputs 3-bit pattern - level sensing (clock pod)
Clock outputs Synchronized to output data, delay of 11 ns in 9 steps
(clock pod)
Clock input DC to 200 MHz (clock pod)
Internal clock period Programmable from 5 ns to 250 µs in a 1, 2, 2.5, 4, 5, 8
sequence
External clock period (user supplied) DC to 200 MHz
External clock duty cycle 2 ns minimum high time
Maximum number of "IF condition" 1
blocks at 50 MHz clock
Maximum number of different macros 100
Maximum number of lines in a macro 1024
Maximum number of macro invocations 1,000
Maximum number of Repeat loop 1,000
invocations
Maximum number of Wait event patterns 4
General Information
Characteristics (pattern generator)
1–6