Notice Hewlett-Packard to Agilent Technologies Transition This manual may contain references to HP or Hewlett-Packard. Please note that HewlettPackard’s former test and measurement, semiconductor products and chemical analysis businesses are now part of Agilent Technologies. To reduce potential confusion, the only change to product numbers and names has been in the company name prefix: where a product name/number was HP XXXX the current name/number is now Agilent XXXX.
Service Guide Publication number 01660-97026 First edition, November 1997 For Safety information, Warranties, and Regulatory information, see the pages at the end of the book. Copyright Hewlett-Packard Company 1987–1997 All Rights Reserved.
HP 1660C-Series, HP 1660CS-Series, and HP 1660CP-Series Logic Analyzers The HP 1660C-Series are 100-MHz State/500 MHz Timing Logic Analyzers. The HP 1660CS-Series includes all the features of the HP 1660C-Series, as well as a 2-channel, 1 GSa/s oscilloscope. The HP 1660CP-Series includes all the features of the HP 1660C-Series, as well as a 32-channel pattern generator.
The HP 1660CS-Series Logic Analyzers also include the following features: • 1 GSa/s digitizing for 250 MHz bandwidth single shot oscilloscope • 8000 samples per channel • Automatic pulse parameters displays time between markers, acquires until specified time between markers is captured, performs statistical analysis on time between markers • Lightweight miniprobes Options The HP 1660C-Series, HP 1660CP-Series, and HP 1660CS-Series Logic Analyzers can be ordered with the optional Thinlan and Ethertwist LAN
In This Book This book is the service guide for the HP 1660C/CS/CP-Series Logic Analyzers and is divided into eight chapters. Chapter 1 contains information about the logic analyzer and includes accessories, specifications and characteristics, and equipment required for servicing. Chapter 2 tells how to prepare the logic analyzer for use. Chapter 3 gives instructions on how to test the performance of the logic analyzer. Chapter 4 contains calibration instructions for the logic analyzer.
Table of Contents 1 General Information Accessories 1–2 Specifications (logic analyzer) 1–3 Specifications (oscilloscope) 1–4 Specifications (pattern generator) 1–4 Characteristics (logic analyzer) 1–5 Characteristics (oscilloscope) 1–5 Characteristics (pattern generator) 1–6 Supplemental Characteristics (logic analyzer) 1–7 Supplemental Characteristics (oscilloscope) 1–10 Recommended test equipment (logic analyzer) 1–14 Recommended test equipment (oscilloscope) 1–15 Recommended test equipment (pattern gen
Contents To test the single-clock, single-edge, state acquisition (logic analyzer) 3–24 Set up the equipment 3–24 Set up the logic analyzer 3–25 Connect the logic analyzer 3–27 Verify the test signal 3–29 Check the setup/hold combination 3–31 Test the next channels 3–36 To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) 3–37 Set up the equipment 3–37 Set up the logic analyzer 3–38 Connect the logic analyzer 3–40 Verify the test signal 3–42 Check the setup/hold with single clock
Contents To test the voltage measurement accuracy (oscilloscope) 3–73 Set up the equipment 3–73 Set up the logic analyzer 3–74 Connect the logic analyzer 3–75 Acquire the data 3–76 To test the offset accuracy (oscilloscope) 3–77 Set up the equipment 3–77 Set up the logic analyzer 3–78 Connect the logic analyzer 3–79 Acquire the zero input data 3–80 Acquire the DC input data 3–81 To test the bandwidth (oscilloscope) 3–82 Set up the equipment 3–82 Set up the logic analyzer 3–83 Connect the logic analyzer 3
Contents 4 Calibrating and Adjusting Logic analyzer calibration 4–2 To calibrate the oscilloscope 4–3 Set up the equipment 4–3 Load the Default Calibration Factors 4–4 Self Cal menu calibrations 4–5 To adjust the CRT monitor alignment 4–6 To adjust the CRT intensity 4–8 5 Troubleshooting To use the flowcharts 5–2 To check the power-up tests 5–17 To run the self-tests 5–18 To test the power supply voltages 5–24 To test the CRT monitor signals 5–26 To test the keyboard signals 5–27 To test the flexible dis
Contents To return assemblies 6–18 7 Replaceable Parts Replaceable Parts Ordering 7–2 Replaceable Parts List 7–3 Exploded View 7–4 Power Cables and Plug Configurations 7–8 8 Theory of Operation Block-Level Theory 8–3 The HP 1660C/CS/CP Series Logic Analyzer 8–3 The Logic Acquisition Board 8–7 The Oscilloscope Board 8–10 The Pattern Generator Board 8–13 Self-Tests Description 8–15 Power-up Self-Tests 8–15 System Tests (System PV) 8–16 Analyzer Tests (Analy PV) 8–20 Oscilloscope tests (Scope PV) 8–22 Patt
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1 Accessories 1–2 Specifications (logic analyzer) 1–3 Specifications (oscilloscope) 1–4 Specifications (pattern generator) 1–4 Characteristics (logic analyzer) 1–5 Characteristics (oscilloscope) 1–5 Characteristics (pattern generator) 1–6 Supplemental Characteristics (logic analyzer) 1–7 Supplemental Characteristics (oscilloscope) 1–10 Recommended test equipment (logic analyzer) 1–14 Recommended test equipment (oscilloscope) 1–15 Recommended test equipment (pattern generator) 1–16 General Information
General Information This chapter lists the accessories, the specifications and characteristics, and the recommended test equipment. Accessories The following accessories are supplied with the HP 1660C/CS/CP-series logic analyzers.
General Information Specifications (logic analyzer) Specifications (logic analyzer) The specifications are the performance standards against which the product is tested. Maximum State Speed 100 MHz * 3.5 ns Minimum State Clock Pulse Width * Minimum Master to Master Clock Time 10.0 ns Minimum Glitch Width* 3.5 ns Threshold Accuracy Setup/Hold Time:* Single Clock, Single Edge Single Clock, Multiple Edges Multiple Clocks, Multiple Edges ± (100 mV + 3% of threshold setting) 0.0/3.5 ns through 3.5/0.
General Information Specifications (oscilloscope) Specifications (oscilloscope) The HP 1660CS Logic Analyzers also include the following specifications: Bandwidth (*,1) DC to 250 MHz (real time, dc-coupled) Time Interval Measurement Accuracy(*, 2) ±[(0.005% X ∆t)+ (2 x 10−6 x delay setting)+150 ps] DC Offset Accuracy(*) ±(1.0% of channel offset + 2.0% of full scale) (*, 3) Voltage Measurement Accuracy Trigger Sensitivity(*) Input R (selectable) (*) ± [(1.5% of full scale + offset accuracy) + (0.
General Information Characteristics (logic analyzer) Characteristics (logic analyzer) These characteristics are not specifications, but are included as additional information.
General Information Characteristics (pattern generator) Characteristics (pattern generator) The HP 1660CP Logic Analyzers also include the following characteristics: Output channels 16 channels at 200 MHz clock; 32 channels at 100 MHz clock Memory depth 258,048 vectors Logic levels (data pods) Data inputs Clock outputs Clock input Internal clock period External clock period (user supplied) External clock duty cycle Maximum number of "IF condition" blocks at 50 MHz clock Maximum number of different macros
General Information Supplemental Characteristics (logic analyzer) Supplemental Characteristics (logic analyzer) Probes Input Resistance Input Capacitance Minimum Voltage Swing Threshold Range 100 kΩ, ± 2% ~ 8 pF 500 mV, peak-to-peak ± 6.
General Information Supplemental Characteristics (logic analyzer) Measurement and Display Functions Displayed Waveforms 24 lines maximum, with scrolling across 96 waveforms. Measurement Functions Run/Stop Functions Run starts acquisition of data in specified trace mode. Stop In single trace mode or the first run of a repetitive acquisition, Stop halts acquisition and displays the current acquisition data.
General Information Supplemental Characteristics (logic analyzer) Marker Functions Time Interval The X and O markers measure the time interval between a point on a timing waveform and the trigger, two points on the same timing waveform, two points on different waveforms, or two states (time tagging on). Delta States (state analyzer only) The X and O markers measure the number of tagged states between one state and trigger or between two states.
General Information Supplemental Characteristics (oscilloscope) Product Regulations Safety EMC Emissions Immunity IEC 1010-1:1990+A1 / EN 61010-1:1993 UL3111 CSA-C22.2 No. 1010.1:1993 This product meets the requirement of the European Communities (EC) EMC Directive 89/336/EEC. EN55011/CSIPR 11 (ISM, Group1,Class A equipment) IEC 555-2 and IEC 555-3 EN50082-1 Code1 Notes2 IEC 801-2 (ESD)4kV CD, 8kV AD 1 IEC 801-3 (Rad.
General Information Supplemental Characteristics (oscilloscope) Timebase Range Resolution Delay Pre-trigger Range 1 ns/div to 5 s/div 20 ps Time/div Setting 1 µs to 5 s/div 1 ns to 500 ns/div Available Delay -8 x (s/div) -4 µs Time/div Setting 100 ms to 5 s/div 1 µs to 50 ms/div 1ns to 500 ns/div Available Delay 2.5 ks 33,500 x (s/div) 16.
General Information Supplemental Characteristics (oscilloscope) Digitizer Resolution Digitizing Rate Digitizing Technique Acquisition Memory Size Waveform Display Displayed Waveforms Display Formats Display Resolution Display Modes Normal (Single) Accumulate Average Overlay Connect-the-dots Waveform Reconstruction Waveform Math 1–12 8 bits (1 part in 256) Up to 1 Gigasample per second Real-time digitizing; each 8000 samples are acquired on a single acquisition 8000 samples per channel Eight waveform
General Information Supplemental Characteristics (oscilloscope) Measurement and Display Functions Time Markers Two vertical markers, X and O, are provided for measurements of time and voltage.
General Information Recommended test equipment (logic analyzer) Recommended test equipment (logic analyzer) Equipment Required Equipment Critical Specifications Pulse Generator 100 MHz, 3.
General Information Recommended test equipment (oscilloscope) Recommended test equipment (oscilloscope) Equipment Required Equipment Critical Specifications Recommended Model/Part Use* Signal Generator Frequency: 1 - 250 MHz at approx. 170 mV RMS Output Accuracy: ± 1 dB 1 MHz time base accuracy 0.25 ppm HP 8656B Option 001 P DC Power Supply Range: −35.000 to +35.000 Vdc, ±1 mV HP 3245A Option 002 P Digital Multimeter 0.1 mV resolution Accuracy: better than 0.
General Information Recommended test equipment (pattern generator) Recommended test equipment (pattern generator) Equipment Required Equipment Critical Specifications Recommended Model/Part Use* Oscilloscope ≥ 500 MHz Bandwidth HP 54522A T Probe 500 MHz Bandwidth HP 10441A T Output Data Pod no substitute 10460A - series T * T = Troubleshooting 1–16
2 To inspect the logic analyzer 2–2 To apply power 2–3 To operate the user interface 2–3 To set the line voltage 2–3 To degauss the display 2–4 To clean the logic analyzer 2–4 To test the logic analyzer 2–4 Preparing for Use
Preparing For Use This chapter gives you instructions for preparing the logic analyzer for use. Power Requirements The logic analyzer power source requirements are either 115 V ac or 230 V ac, –22 % to +10 %, single phase, 48 to 66 Hz, 200 Watts maximum power. Operating Environment The operating environment is listed in chapter 1. Note the noncondensing humidity limitation listed below. Condensation within the instrument can cause poor operation or malfunction.
Preparing for Use To apply power To apply power 1 Check that the line voltage selector, located on the rear panel, is on the correct setting and the correct fuse is installed. See also, "To set the line voltage" on this page. 2 Connect the power cord to the instrument and to the power source. This instrument is equipped with a three-wire power cable. When connected to an appropriate AC power outlet, this cable grounds the instrument cabinet.
Preparing for Use To degauss the display 3 Reinsert the fuse module with the arrow for the appropriate line voltage aligned with the arrow on the line filter assembly switch. 4 Reconnect the power cord. Turn on the instrument by setting the power switch to the On position. To degauss the display If the logic analyzer has been subjected to strong magnetic fields, the CRT might become magnetized and display data might become distorted.
3 To perform the self-tests 3–3 To make the test connectors (logic analyzer) 3–7 To test the threshold accuracy (logic analyzer) 3–9 To test the glitch capture (logic analyzer) 3–18 To test the single-clock, single-edge, state acquisition (logic analyzer) 3–24 To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) 3–37 To test the single-clock, multiple-edge, state acquisition (logic analyzer) 3–49 To test the time interval accuracy (logic analyzer) 3–60 To test the CAL OUTPUT ports
Testing Performance This chapter tells you how to test the performance of the logic analyzer against the specifications listed in chapter 1. To ensure the logic analyzer is operating as specified, you perform software tests (self-tests) and manual performance tests on the analyzer. The logic analyzer is considered performance-verified if all of the software tests and manual performance tests have passed. The procedures in this chapter indicate what constitutes a "Pass" status for each of the tests.
To perform the self-tests The self-tests verify the correct operation of the logic analyzer. Self-tests can be performed all at once or one at a time. While testing the performance of the logic analyzer, run the self-tests all at once. The performance verification (PV) self-tests consist of system PV tests, analyzer PV tests, and oscilloscope PV tests (HP 1660CS series only). These procedures assume the files on the PV disk have been copied to the /SYSTEM subdirectory on the hard disk drive.
Testing Performance To perform the self-tests 5 Install a formatted disk that is not write-protected into the disk drive. Connect an RS-232-C loopback connector onto the RS-232-C port. 6 Select All System Tests. You can run all tests at one time, except for the Front Panel Test and Display Test, by running All System Tests. To see more details about each test when troubleshooting failures, you can run each test individually. This example shows how to run all tests at once.
Testing Performance To perform the self-tests 9 Select Sys PV, then select Analy PV in the pop-up menu. In the Analy PV menu, Select All Analyzer Tests. You can run all tests at one time, except for the Data Input Inspection, by running All Analyzer Tests. To see more details about each test when troubleshooting failures, you can run each test individually. This example shows how to run all tests at once.
Testing Performance To perform the self-tests 13 For the HP 1660CS-series Logic Analyzers, Select Analy PV, then select Scope PV in the pop-up menu. In the Scope PV menu, select Functional Tests then select All Tests. You can run all tests at one time, except for the Data Input Inspection, by running All Tests. To see more details about each test when troubleshooting failures, you can run each test individually. This example shows how to run all tests at once.
To make the test connectors (logic analyzer) The test connectors connect the logic analyzer to the test equipment. The following materials are required to make the test connectors. Materials Required Description Recommended Part Qty BNC (f) Connector HP 1250-1032 5 100 Ω 1% resistor HP 0698-7212 8 Berg Strip, 17-by-2 1 Berg Strip, 6-by-2 4 20:1 Probe HP 54006A 2 Jumper wire 1 Build four test connectors using BNC connectors and 6-by-2 sections of Berg strip.
Testing Performance To make the test connectors (logic analyzer) 2 Build one test connector using a BNC connector and a 17-by-2 section of Berg strip. a Solder a jumper wire to all pins on one side of the Berg strip. b Solder a jumper wire to all pins on the other side of the Berg strip. c Solder the center of the BNC connector to the center pin of one row on the Berg strip. d Solder the ground tab of the BNC connector to the center pin of the other row on the Berg strip.
To test the threshold accuracy (logic analyzer) Testing the threshold accuracy verifies the performance of the following specification: • Clock and data channel threshold accuracy. These instructions include detailed steps for testing the threshold settings of pod 1. After testing pod 1, connect and test the rest of the pods one at a time. To test the next pod, follow the detailed steps for pod 1, substituting the next pod for pod 1 in the instructions.
Testing Performance To test the threshold accuracy (logic analyzer) Set up the logic analyzer 1 Press the Config key. 2 Unassign Pods 3 and 4, Pods 5 and 6, and Pods 7 and 8. To unassign the pods, select the pod field. In the pop-up menu, select Unassigned. Connect the logic analyzer 1 Using the 17-by-2 test connector, BNC cable, and probe tip assembly, connect the data and clock channels of pod 1 to one side of the BNC Tee.
Testing Performance To test the threshold accuracy (logic analyzer) Test the TTL threshold 1 Press the Format key. Select the field to the right of Pod A1, then select TTL in the pop-up menu. 2 On the function generator front panel, enter 1.750 V ±1 mV DC offset. Use the multimeter to verify the voltage. The activity indicators for pod 1 should show all data channels and the J-clock channel at a logic high.
Testing Performance To test the threshold accuracy (logic analyzer) 4 Using the Modify up arrow on the function generator, increase offset voltage in 1-mV increments until all activity indicators for pod 1 show the channels at a logic high. Record the function generator voltage in the performance test record.
Testing Performance To test the threshold accuracy (logic analyzer) Test the ECL threshold 1 Select the field to the right of Pod A1, then select ECL in the pop-up menu. 2 On the function generator front panel, enter −1.160 V ±1 mV DC offset. Use the multimeter to verify the voltage. The activity indicators for pod 1 should show all data channels and the J-clock channel at a logic high.
Testing Performance To test the threshold accuracy (logic analyzer) Test the − User threshold 1 Move the cursor to the field to the right of Pod A1. Type –6.00, then use the left and right cursor control keys to highlight V. Press the Select key. 2 On the function generator front panel, enter −5.718 V ±1 mV DC offset. Use the multimeter to verify the voltage. The activity indicators for pod 1 should show all data channels and the J-clock channel at a logic high.
Testing Performance To test the threshold accuracy (logic analyzer) Test the + User threshold 1 Move the cursor to the field to the right of Pod A1. Type +6.00, then use the left and right cursor control keys to highlight V. Press the Select key. 2 On the function generator front panel, enter +6.282 V ±1 mV DC offset. Use the multimeter to verify the voltage. The activity indicators for pod 1 should show all data channels and the J-clock channel at a logic high.
Testing Performance To test the threshold accuracy (logic analyzer) Test the 0 V User threshold 1 Move the cursor to the field to the right of Pod A1. Type 0, then press the Select key. 2 On the function generator front panel, enter +0.102 V ±1 mV DC offset. Use the multimeter to verify the voltage. The activity indicators for pod 1 should show all data channels and the J-clock channel at a logic high.
Testing Performance To test the threshold accuracy (logic analyzer) Test the next pod 1 Using the 17-by-2 test connector and probe tip assembly, connect the data and clock channels of the next pod to the output of the function generator until all pods have been tested. To unassign a pod pair and assign the next pod pair to be tested, press the Config key. Select the pod pairs, then select assign or unassign in the pop-up menu.
To test the glitch capture (logic analyzer) Testing the glitch capture verifies the performance of the following specification: • Minimum detectable glitch. This test checks the minimum detectable glitch on sixteen data channels at a time. Equipment Required Equipment Pulse Generator Digitizing Oscilloscope SMA Coax (Qty 3) Adapter (Qty 4) Coupler (Qty 4) BNC Test Connector, 6x2 (Qty 4) Critical Specifications 100 MHz 3.
Testing Performance To test the glitch capture (logic analyzer) 3 Set up the oscilloscope. Oscilloscope Setup Time Base Display Delta V Delta T Time/Div: 1.00 ns/div mode: avg V markers on T markers on delay: 17.7000 ns # of avg: 16 marker 1 position: Chan 1 start on: Pos Edge 1 screens: dual marker 2 position: Chan 2 stop on: Pos Edge 1 Channel 1 Channel 2 Display on on Probe Atten 20.00 20.00 Volts/Div 400 mV 400 mV Offset −1.3000 V −1.
Testing Performance To test the glitch capture (logic analyzer) The table includes all the HP 1660C/CS/CP Series.
Testing Performance To test the glitch capture (logic analyzer) Test the glitch capture on the connected channels 1 Set up the Format menu. a Press the Format key. b Select the field to the right of each pod, then select ECL in the pop-up menu. Use the knob to access pods not shown on the screen (to activate the knob for pods, use the cursor to select the Pods field and push Select). c Select Timing Acquisition Mode, then select Glitch Half Channel 125 MHz.
Testing Performance To test the glitch capture (logic analyzer) 3 Set up the Trigger menu. a Press the Trigger key. b Select Modify Trigger, then select Clear Trigger, then select All. 4 Using the [Shift] + width: channel 1 and [Shift] + width: channel 2 of the oscilloscope, verify that the pulse widths of the pulse generator channels 1 and 2 are 3.450 ns, +50 ps or −100 ps. If necessary, adjust the pulse widths of the pulse generator channels 1 and 2.
Testing Performance To test the glitch capture (logic analyzer) 6 On the logic analyzer, press the Run key. The display should be similar to the figure below. 7 On the pulse generator, enable Channel 1 and Channel 2 COMP (with the LED on). 8 On the logic analyzer, press the Run key. The display should be similar to the figure below. Record Pass or Fail in the performance test record.
To test the single-clock, single-edge, state acquisition (logic analyzer) Testing the single-clock, single-edge, state acquisition verifies the performance of the following specifications: • • • • Minimum master-to-master clock time Maximum state acquisition speed Setup/Hold time for single-clock, single-edge, state acquisition Minimum clock pulse width This test checks two combinations of data channels using a single-edge clock at three selected setup/hold times.
Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) 3 Set up the oscilloscope. If the oscilloscope was not configured for the previous test, then do the following steps. a Select Setup, then select Default Setup. b Configure the oscilloscope according to the following table.
Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) 2 Set up the Format menu. a Press the Format key. Select State Acquisition Mode, then select Full Channel/4K Memory/100MHz. b Select the field to the right of each pod, then select ECL in the pop-up menu. Use the knob to access pods not shown on the screen. 3 Set up the Trigger menu. a Press the Trigger key. Select Modify Trigger, select Clear Trigger, then select All in the pop-up menu. b Select Count Off.
Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) Connect the logic analyzer 1 Using the 6-by-2 test connectors, connect the first combination of logic analyzer clock and data channels listed in one of the following tables to the pulse generator. If you are testing an HP 1660C or HP 1661C, you will repeat this test for the second combination. 2 Using SMA cables, connect the oscilloscope to the pulse generator channel 1 Output, channel 2 Output, and Trig Output.
Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) Connect the HP 1662C or HP 1663C Logic Analyzer to the Pulse Generator Testing Combination Connect to HP 8133A Channel 2 Output Connect to HP 8133A Channel 2 Output Connect to HP 8133A Channel 1 Output 1 Pod 1, channel 3 Pod 2, channel 3 Pod 3, channel 3 Pod 4, channel 3 Pod 1, channel 11 Pod 2, channel 11 Pod 3, channel 11 Pod 4, channel 11 J-clock 3 Activate the data channels that are connected according
Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) Verify the test signal 1 Check the clock pulse width. Using the oscilloscope, verify that the clock pulse width is 3.500 ns, +0 ps or −100 ps. a Enable the pulse generator channel 1, channel 2, and trigger outputs (LED off). b In the oscilloscope Timebase menu, select Scale: 1.000 ns/div. c In the oscilloscope Timebase menu, select Position.
Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) 3 Check the data pulse width. Using the oscilloscope, verify that the data pulse width is 3.500 ns, +0 ps or −100 ps. a On the Oscilloscope, select [Define meas] Define ∆ Time - Stop edge: rising. b In the oscilloscope timebase menu, select Position. Using the oscilloscope knob, position the rising edge of the clock waveform so that it is centered on the display.
Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) Check the setup/hold combination 1 Select the logic analyzer setup/hold time. a In the logic analyzer Format menu, select Master Clock. b Select the Setup/Hold field, then select the setup/hold combination to be tested for all pods. The first time through this test, use the top combination in the following table. Setup/Hold Combinations 3.5/0.0 ns 0.0/3.5 ns 1.5/2.
Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) 2 Disable the pulse generator channel 1 COMP (with the LED off). 3 Using the Delay mode of the pulse generator channel 1, position the pulses according to the setup time of the setup/hold combination selected, +0.0 ps or −100 ps. a On the Oscilloscope, select [Define meas] Define ∆ Time - Stop edge: rising. b In the oscilloscope timebase menu, select Position.
Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) 4 Select the clock to be tested. a In the Master Clock menu, select the clock field to be tested, then select the clock edge as indicated in the table. The first time through this test, use the top clock and edge in the following table. Clocks J↑ K↑ L↑ M↑ N↑ P↑ b Connect the clock to be tested to the pulse generator channel 2 output. c Select Done to exit the Master Clock menu.
Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) 5 Note: This step is only done the first time through the test, to create a Compare file. For subsequent runs, go to step 6. Use the following to create a Compare file: a Press Run. The display should show an alternating pattern of "AA" and "55". Verify the pattern by scrolling through the display. b Press the List key. In the pop-up menu, use the RPG knob to move the cursor to Compare. Press Select.
Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) 10 Using the Delay mode of the pulse generator channel 1, position the pulses according to the setup/hold combination selected, +0.0 ps or −100 ps. a On the Oscilloscope, select [Define meas] Define ∆ Time - Stop edge: falling. b On the oscilloscope, select [Shift] - width: channel 2, then select [Enter] to verify the clock signal pulse width (- width(2)).
Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) 12 Press the blue shift key, then press the Run key. If two to four acquisitions are obtained without the "Stop Condition Satisfied" message appearing, then the test passes. Press Stop to halt the acquisition. Record the Pass or Fail results in the performance test record. 13 Test the next clock. a Press the Format key, then select Master Clock. b Turn off and disconnect the clock just tested.
To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) Testing the multiple-clock, multiple-edge, state acquisition verifies the performance of the following specifications: • • • • Minimum master to master clock time Maximum state acquisition speed Setup/Hold time for multiple-clock, multiple-edge, state acquisition Minimum clock pulse width This test checks two combinations of data using multiple clocks at three selected setup/hold times.
Testing Performance To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) 3 Set up the oscilloscope. If the oscilloscope was not configured for the previous test, then do the following steps. a Select Setup, then select Default Setup. b Configure the oscilloscope according to the following table.
Testing Performance To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) 2 Set up the Format menu. a Press the Format key. Select State Acquisition Mode, then select Full Channel/4K Memory/100MHz. b Select the field to the right of each Pod field, then select ECL. The screen does not show all Pod fields at one time. Use the knob to access more Pod fields. 3 Set up the Trigger menu. a Press the Trigger key. Select Modify Trigger, then select Clear Trigger, then select All.
Testing Performance To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) Connect the logic analyzer 1 Using the 6-by-2 test connectors, connect the first combination of logic analyzer clock and data channels listed in one of the following tables to the pulse generator. If you are testing an HP 1660C or HP 1661C, you will repeat this test for the second combination. 2 Using SMA cables, connect channel 1, channel 2, and trigger of the oscilloscope to the pulse generator.
Testing Performance To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) Connect the HP 1662C/CS/CP or HP 1663C/CS/CP Logic Analyzer to the Pulse Generator Testing Combination Connect to HP 8133A Channel 2 Output Connect to HP 8133A Channel 2 Output Connect to HP 8133A Channel 1 Output 1 Pod 1, channel 3 Pod 2, channel 3 Pod 3, channel 3 Pod 4, channel 3 Pod 1, channel 11 Pod 2, channel 11 Pod 3, channel 11 Pod 4, channel 11 J-clock K-clock L-clock M-clock 3 Activate the da
Testing Performance To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) Verify the test signal 1 Check the clock pulse width. Using the oscilloscope, verify that the clock pulse width is 3.500 ns, +0 ps or −100 ps. a Enable the pulse generator channel 1, channel 2, and trigger outputs (LED off). b In the oscilloscope Timebase menu, select Scale: 1.000 ns/div. c In the oscilloscope Timebase menu, select Position.
Testing Performance To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) 3 Check the data pulse width. Using the oscilloscope verify that the data pulse width is 4.500 ns, +0 ps or −100 ps. a In the oscilloscope Timebase menu, select Scale: 1.000 ns/div. b In the oscilloscope Timebase menu, select Position. Using the oscilloscope knob, position the data waveform so that the waveform is centered on the screen.
Testing Performance To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) Check the setup/hold with single clock edges, multiple clocks 1 Select the logic analyzer setup/hold time. a In the logic analyzer Format menu, select Master Clock. b Select and activate any two clock edges. c Select the Setup/Hold field and select the setup/hold to be tested for all pods. The first time through this test, use the top combination in the following table. Setup/Hold Combinations 4.5/0.0 ns 0.
Testing Performance To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) d Adjust the pulse generator channel 1 Delay until the pulses are aligned according the the setup time of the setup/hold combination selected, +0.0 ps or -100 ps. 4 Select the clocks to be tested. a Select the clock field to be tested and then select the clock edges as indicated in the table. The first time through this test, use the top clocks and edges (HP 1660C/CS/CP and HP 1661C/CS/CP).
Testing Performance To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) 5 If you have not already created a Compare file for the previous test (single-clock, single-edge state acquisition, page 32), use the following steps to create one. For subsequent passes through this test, skip this step and go to step 6. a Press Run. The display should show an alternating pattern of "AA" and "55". Verify the pattern by scrolling through the display. b Press the List key.
Testing Performance To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) 9 Using the Delay mode of the pulse generator channel 1, position the pulses according to setup time of the setup/hold combination selected, +0.0 ps or −100 ps. a On the Oscilloscope, select [Define meas] Define ∆ Time - Stop edge: falling. b On the oscilloscope, select [Shift] - width: channel 2, then select [Enter] to verify the clock signal pulse width (- width (2)).
Testing Performance To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) 11 Press the blue shift key, then press the Run key. If 2 - 4 acquisitions are obtained without the "Stop Condition Satisfied" message appearing, then the test passes. Press Stop to halt the acquisition. Record the Pass or Fail results in the performance test record. 12 Test the next clocks. a In the logic analyzer Format menu, select Master Clock. b Turn off and disconnect the clocks just tested.
To test the single-clock, multiple-edge, state acquisition (logic analyzer) Testing the single-clock, multiple-edge, state acquisition verifies the performance of the following specifications: • • • • Minimum master to master clock time Maximum state acquisition speed Setup/Hold time for single-clock, multiple-edge, state acquisition Minimum clock pulse width This test checks two combinations of data using a multiple-edge single clock at three selected setup/hold times.
Testing Performance To test the single-clock, multiple-edge, state acquisition (logic analyzer) 3 Set up the oscilloscope. If the oscilloscope was not configured for the previous test, then do the following steps. a Select Setup, then select Default Setup. b Configure the oscilloscope according to the following table.
Testing Performance To test the single-clock, multiple-edge, state acquisition (logic analyzer) 2 Set up the Format menu. a Press the Format key. Select State Acquisition Mode, then select Full Channel/4K Memory/100MHz. b Select the field to the right of each pod field, then select ECL. The screen does not show all pod fields at one time. Use the knob to access pod fields not shown on the screen. 3 Set up the Trigger menu. a Press the Trigger key.
Testing Performance To test the single-clock, multiple-edge, state acquisition (logic analyzer) Connect the logic analyzer 1 Using the 6-by-2 test connectors, connect the first combination of logic analyzer clock and data channels listed in one of the following tables to the pulse generator. If you are testing an HP 1660C or HP 1661C, you will repeat this test for the second combination. 2 Using the SMA cables, connect channel 1, channel 2, and trigger from the oscilloscope to the pulse generator.
Testing Performance To test the single-clock, multiple-edge, state acquisition (logic analyzer) Connect the HP 1662C/CS/CP or HP 1663C/CS/CP Logic Analyzer to the Pulse Generator Testing Combination Connect to HP 8133A Channel 2 Output Connect to HP 8133A Channel 2 Output Connect to HP 8133A Channel 1 Output 1 Pod 1, channel 3 Pod 2, channel 3 Pod 3, channel 3 Pod 4, channel 3 Pod 1, channel 3 Pod 2, channel 3 Pod 3, channel 3 Pod 4, channel 3 J-clock 3 Activate the data channels that are connected
Testing Performance To test the single-clock, multiple-edge, state acquisition (logic analyzer) Verify the test signal 1 Check the clock period. Using the oscilloscope, verify that the master-to-master clock time is 10.000 ns, +0 ps or -250 ps. a Enable the pulse generator channel 1, channel 2, and trigger outputs (LED off). b In the oscilloscope Timebase menu, select Scale: 2.500 ns/div. c In the oscilloscope Timebase menu, select Position.
Testing Performance To test the single-clock, multiple-edge, state acquisition (logic analyzer) 2 Check the data pulse width. Using the oscilloscope, verify that the data pulse width is 4.000 ns, +0 ps or −100 ps. a In the oscilloscope Timebase menu, select Scale: 1.000 ns/div. b In the oscilloscope Timebase menu, select Position. Using the oscilloscope knob, position the data waveform so that the waveform is centered on the screen.
Testing Performance To test the single-clock, multiple-edge, state acquisition (logic analyzer) Check the setup/hold with single clock, multiple clock edges 1 Select the logic analyzer setup/hold time. a In the logic analyzer Format menu, select Master Clock. b Select and activate any multiple clock edge. c Select the Setup/Hold field, then select the setup/hold to be tested for all pods. The first time through this test, use the top combination in the following table. Setup/Hold Combinations 4.0/0.0 ns 0.
Testing Performance To test the single-clock, multiple-edge, state acquisition (logic analyzer) d Adjust the pulse generator channel 2 Delay until the pulses are aligned according the the setup time of the setup/hold combination selected, +0.0 ps or -100 ps. 3 Select the clock to be tested. a Select the clock field to be tested, then select the clock as indicated in the table. The first time through this test, use the top multiple-edge clock in the following table.
Testing Performance To test the single-clock, multiple-edge, state acquisition (logic analyzer) 4 If you have not already created a Compare file for the previous test (single-clock, single-edge state acquisition, page 32), use the following steps to create one. For subsequent passes through this test, skip this step and go to step 5. a Press Run. The display should show an alternating pattern of "AA" and "55". Verify the pattern by scrolling through the display. b Press the List key.
Testing Performance To test the single-clock, multiple-edge, state acquisition (logic analyzer) 7 Test the next setup/hold combination. a In the logic analyzer Format menu, select Master Clock. b Turn off and disconnect the clock just tested. c Repeat steps 1 through 6 for the next setup/hold combination listed in step 1 on page 3–54, until all listed setup/hold combinations have been tested.
To test the time interval accuracy (logic analyzer) Testing the time interval accuracy does not check a specification, but does check the following: • 125 MHz oscillator This test verifies that the 125 MHz timing acquisition synchronizing oscillator is operating within limits. Equipment Required Equipment Critical Specifications Recommended Model/Part Pulse Generator 100 MHz 3.
Testing Performance To test the time interval accuracy (logic analyzer) 3 Set up the function generator according to the following table. Function Generator Setup Freq: 40.000 00 MHz Amptd: 1.00 V Modulation: Off Set up the logic analyzer 1 Set up the Configuration menu. a Press the Config key. b In the Configuration menu, assign Pod 1 to Machine 1. To assign Pod 1, select the Pod 1 field, then select Machine 1. c In the Analyzer 1 box, select the Type field, then select Timing.
Testing Performance To test the time interval accuracy (logic analyzer) 2 Set up the Format menu. a Press the Format key. Select Timing Acquisition Mode, then select Conditional Halt Channel 500 MHz. b Select the field to the right of the Pod 1 field, then select ECL. c Select the field showing the channel assignments for Pod 1. Deactivate all channels by pressing the Clear entry key. Using the arrow keys, move the selector to Channel 0.
Testing Performance To test the time interval accuracy (logic analyzer) 4 Set up the Waveform menu. a Press the Waveform key. b Move the cursor to the sec/Div field, then use the RPG knob to dial in 100 ns. c Select the Markers Off field, then select Pattern. d Select the Specify Patterns field. Select X entering 1 and O entering 1. e f g h Select Done to exit the Specify Patterns menu. Move the cursor to the X-pat field. Type 1, then press Done. Move the cursor to the O-pat field.
Testing Performance To test the time interval accuracy (logic analyzer) Connect the logic analyzer 1 Using a 6-by-2 test connector, connect channel 0 of Pod 1 to the pulse generator channel 1 output. 2 Using the SMA cable and the BNC adapter, connect the External Input of the pulse generator to the Main Signal of the function generator. Acquire the data 1 Enable the pulse generator channel 1 output (with the LED off). 2 Press the blue key, then press the Run key to select Run-Repetitive.
To test the CAL OUTPUT ports (oscilloscope) Testing the CAL OUTPUT ports does not check a specification, but does check the following: • DC CAL OUTPUT voltage • AC CAL OUTPUT voltage This test verifies that the CAL OUTPUT voltages are operating within limits, so that they can provide accurate calibration for the instrument operational accuracy calibration and probe calibration. Equipment Required Equipment Critical Specifications Recommended Model/Part Digital Multimeter 0.
Testing Performance To test the CAL OUTPUT ports (oscilloscope) Set up the logic analyzer 1 Set up the Calibration menu. a Press the Waveform key. b Press the Waveform key again. At the pop up, select Scope Calibration. c Select the Mode field, then select Service Cal. d Select the Procedure field, then select DC Cal BNC. e Select the DC volts field, and set it to O V.
Testing Performance To test the CAL OUTPUT ports (oscilloscope) Verify the DC CAL OUTPUT port 1 Using the BNC-to-banana adapter, connect the BNC cable between the multimeter and the oscilloscope DC CAL OUTPUT connector. 2 The digital voltmeter should read close to 0.0000 V. Record the reading to four decimal places. V1 = _______. 3 In the Calibration menu set the DC Volts to 5 V. 4 The digital voltmeter should read close to 5.0000 V. Record the reading to four decimal places. V2 = _______.
Testing Performance To test the CAL OUTPUT ports (oscilloscope) Set up the logic analyzer 1 Set up the Calibration menu. a Select the Procedure field, then select Osc Out. b Select the Signal field, then select Probe Comp. 2 Set up the Channel menu. a Press the Chan key. b Select the Coupling field, then select 1MΩ / DC. c Move the cursor to the Probe field, then use the RPG knob to dial in 1:1.
To test the input resistance (oscilloscope) Testing the input resistance verifies the performance of the following specification: • Input resistance This test checks the input resistance at the 50 Ω and 1 MΩ settings in the Coupling field. Equipment Required Equipment Critical Specifications Recommended Model/Part Digital Multimeter Measure resistance (4-wire) better than 0.
Testing Performance To test the input resistance (oscilloscope) Set up the logic analyzer 1 Set up the Channel menu. a Press the Config key. b At the pop up menu, select Scope Channel. c Select the Input field, then select C1. d Move the cursor to the Probe field, then use the RPG knob to dial in 1:1. e Move the cursor to the V/Div field, then use the RPG knob to dial in 20 mV. f Move the cursor to the Offset field. Set the Offset to 0 V by typing 0, then pressing the Select key.
Testing Performance To test the input resistance (oscilloscope) Connect the logic analyzer Using the BNC-to-banana adapters, connect one end of each BNC cable to the 4-wire resistance connections on the multimeter, and connect the free ends of the cables to the BNC Tee. Connect the male end of the BNC tee to the channel 1 input of the oscilloscope module.
Testing Performance Perform an operational accuracy calibration Acquire the data 1 Press the RUN key. The clicking of attenuator relays should be audible. Verify 2 3 4 5 6 7 8 See Also resistance readings on the digital multimeter of 50 Ω ± 0.5 Ω (49.5 to 50.5 Ω). Record the reading in the performance test record. In the Channel menu change the Coupling field to 1MΩ / DC. The clicking of attenuator relays should be audible. Press the RUN key.
To test the voltage measurement accuracy (oscilloscope) Testing the voltage measurement accuracy verifies the performance of the following specification: • Voltage measurement accuracy This test verifies the DC voltage measurement accuracy of the instrument, using a dual cursor measurement that nullifies offset error. Equipment Required Equipment Critical Specifications Recommended Model/Part DC Power Supply –14 Vdc to +14 Vdc, 0.1 mV resolution HP 6114A Digital Multimeter Better than 0.
Testing Performance To test the voltage measurement accuracy (oscilloscope) Set up the logic analyzer 1 Set up the Channel menu. a Press the Config key. In the pop up menu, select Scope Channel. b Select the Input field, then select C1. c Move the cursor to the Probe field, then use the RPG knob to dial in 1:1. d Select the Coupling field, then select 1MΩ / DC. e Move the cursor to the s/Div field, then use the RPG knob to dial in 500 ns.
Testing Performance To test the voltage measurement accuracy (oscilloscope) 4 Set up the Marker menu. a Press the Marker key. b Move the cursor to the V Markers field and press Select. The voltage markers should now be On. c Select Va on C1. d Select Vb on C1. e If the T markers are On, turn the T markers Off by moving the cursor to the T markers field and pressing Select. Select Off. Connect the logic analyzer 1 Using a BNC-to-banana adapter, connect one end of the cable to the power supply.
Testing Performance To test the voltage measurement accuracy (oscilloscope) Acquire the data Use the following table for steps 1 through 5. Oscilloscope Settings V/Div Offset Voltage Readings Supply Upper Limit Lower Limit 4 V/Div -7.0 V -14.0 V -13.7 V -14.3 V 1 V/Div -1.75 V -3.50 V -3.43 V -3.57 V 400 mV/Div -700.0 mV -1.40 V -1.37 V -1.43 V 40 mV/Div -70.0 mV -140.0 mV -137.0 mV -143.0 mV 40 mV/Div 70.0 mV 140.0 mV 143.0 mV 137.0 mV 400 mV/Div 700.0 mV 1.40 V 1.43 V 1.
To test the offset accuracy (oscilloscope) Testing the offset accuracy verifies the performance of the following specification: • Offset accuracy Equipment Required Equipment Critical Specifications Recommended Model/Part DC Power Supply −35.000 to +35.000 Vdc, ± 1 mV resolution HP 6114A Digital Multimeter Better than 0.
Testing Performance To test the offset accuracy (oscilloscope) Set up the logic analyzer 1 Set up the Configuration menu. a Press the Config key. At the pop up menu, select Scope Channel. b Select the Input field, then select C1. c Move the cursor to the Probe field, then use the RPG knob to dial in 1:1. d Move the cursor to the V/Div field, then use the PRG knob to dial in 4.00 V. e Move the cursor to the Offset field. Set the offset to 0 by typing 0, then pressing the Select key.
Testing Performance To test the offset accuracy (oscilloscope) 3 Set up the Trigger menu. a Press the Trigger key. b Select the Mode/Arm field, then select Immediate. 4 Set up the Marker menu. a Press the Marker key. b Move the cursor to the T Markers field. Press Select, and then press On. c If the V markers are On, turn the V markers Off by moving the cursor to the V markers field and pressing Select.
Testing Performance To test the offset accuracy (oscilloscope) Acquire the zero input data 1 Disconnect the power supply from the channel input. 2 Press the Chan key. Move the cursor to the V/Div field and press the Select key. 3 Press the blue shift key, then press the Run key. After approximately 15 seconds (averaging complete), press the Stop key. Read the voltage from the Markers voltage field (0.00 V ± 320 mV) and enter the value in the performance test record. 4 Use the RPG knob to dial in 1 V/Div.
Testing Performance To test the offset accuracy (oscilloscope) Acquire the DC input data Use the following table for steps 1 through 5. Multimeter Settings Scope Settings Power Supply Settings Scope Readings V/Div Offset Supply Minimum Maximum 1 V/Div −35.00 V −35.00 V −35.4 V −34.6 V 200 mV/Div −10.00 V −10.00 V −10.1 V −9.90 V 20 mV/Div −2.00 V −2.00 V −2.02 V −1.98 V 20 mV/Div +2.00 V +2.00 V +1.98 V +2.02 V 200 mV/Div +10.00 V +10.00 V +9.90 V +10.1 V 1 V/Div +35.
To test the bandwidth (oscilloscope) Testing the bandwidth verifies the performance of the following specification: • Bandwidth This test verifies the bandwidth (dc coupled) of the instrument from dc to 250 MHz. Equipment Required Equipment Critical Specifications Recommended Model/Part Signal Generator 1 - 250 MHz at approximately 170 mV rms HP 8656B Power Meter/Sensor 1 - 250 MHz ± 3% accuracy HP 436/8482A Power Splitter Outputs differ by <0.
Testing Performance To test the bandwidth (oscilloscope) Set up the logic analyzer 1 Set up the Configuration menu. a Press the Config key. At the pop up menu, select Scope Channel. b Select the Input field, then select C1. c Move the cursor to the Probe field, then use the RPG knob to dial in 1:1. d Move the cursor to the V/Div field. Type 80 on the front-panel keyboard, then use the left and right control keys to select mV. Press the Select key. e Move the cursor to the Offset field.
Testing Performance To test the bandwidth (oscilloscope) 3 Set up the Trigger menu. a Press the Trigger key. b Select the Mode/Arm field, then select Edge. c Select the Source field, then select C1. d Move the cursor to the Level field. Set the trigger level to 0 by typing 0 in the front-panel keyboard, then pressing Select. 4 Turn off the voltage and time markers. a Press the Marker key. b Move the cursor to the V Markers field and press Select. The Select key should toggle the marker to Off.
Testing Performance To test the bandwidth (oscilloscope) Connect the logic analyzer 1 Using the N cable, connect the signal generator to the power splitter input. Connect the power sensor to one output of the power splitter. 2 Using the N-to-BNC adapter and the BNC cable, connect the other power splitter output to the channel 1 input of the oscilloscope.
Testing Performance To test the bandwidth (oscilloscope) Acquire the data 1 Obtain the 1 MHz response. a Set the signal generator for 1 MHz at −2.4 dBm. b Press the blue shift key, then press the Run key. The signal on the screen should be two cycles at three divisions amplitude. After approximately 15 seconds (averaging complete), press the Stop key. c Press the Meas key. Note the voltage reading in the Vp-p field. V1 MHz = __________ mV. 2 Set the signal generator for 250 MHz frequency.
To test the time measurement accuracy (oscilloscope) Testing the time measurement accuracy verifies the performance of the following specification: • Time Measurement accuracy This test uses a precise frequency source to check the accuracy of time measurement functions. Equipment Required Equipment Critical Specifications Recommended Model/Part Signal Generator 200 MHz, timebase accuracy 0.25 ppm HP 8656B Opt.
Testing Performance To test the time measurement accuracy (oscilloscope) Set up the logic analyzer 1 Set up the Configuration menu. a Press the Config key. At the pop up menu, select Scope Channel. b Select the Input field, then select C1. c Move the cursor to the Probe field, then use the RPG knob to dial in 1:1. d Move the cursor to the V/Div field, then use the PRG knob to dial in 400 mV. e Move the cursor to the Offset field. Set the offset to 0 by typing 0, then pressing the Select key.
Testing Performance To test the time measurement accuracy (oscilloscope) 3 Set up the Trigger menu. a Press the Trigger key. b Select the Mode/Arm field, then select Edge. c Select the Source field and set it to C1. d Move the cursor to the Level field. Set the trigger level to 0 by typing 0 in the front-panel keyboard, then pressing Select. e Select the Slope field and set it to Positive. 4 Set up the Markers menu. a Press the Marker key. b Move the cursor to the T Markers field and press Select.
Testing Performance To test the time measurement accuracy (oscilloscope) Connect the logic analyzer Using the N-to-BNC adapter and the BNC cable, connect the signal generator output to the channel 1 input of the oscilloscope. Acquire the data 1 Determine short time period accuracy. a Press the blue shift key, then press Run. If the waveform is clipping, reduce the signal generator output voltage level until the waveform no longer clips. After approximately two minutes, press the Stop key.
To test the trigger sensitivity (oscilloscope) Testing the trigger sensitivity verifies the performance of the following specifications: • DC to 50 MHz: 0.063 x full scale (0.25 division) • 50 MHz to 250 MHz: 0.125 x full scale (0.5 division) Equipment Required Equipment Critical Specifications Recommended Model/Part Signal Generator 50 MHz and 225 MHz, 30 - 80 mV RMS output HP 8656B Opt.
Testing Performance To test the trigger sensitivity (oscilloscope) Set up the logic analyzer 1 Set up the Configuration menu. a Press the Config key. At the pop up menu, select Scope Channel. b Select the Input field, then select C1. c Move the cursor to the Probe field, then use the RPG knob to dial in 1:1. d Move the cursor to the V/Div field, then use the PRG knob to dial in 400 mV. e Move the cursor to the Offset field. Set the offset to 0 by typing 0, then pressing the Select key.
Testing Performance To test the trigger sensitivity (oscilloscope) 3 Set up the Trigger menu. a Press the Trigger key. b Select the Mode/Arm field, then select Edge. c Select the Source field and set it to C1. d Move the cursor to the Level field. Set the trigger level to 0 by typing 0 in the front-panel keyboard, then pressing Select. 4 Turn off the voltage and time markers. a Press the Marker key. b Move the cursor to the V Markers field and press Select. The Select key should toggle the marker to Off.
Testing Performance To test the trigger sensitivity (oscilloscope) Connect the logic analyzer Using the N-to-BNC adapter and the BNC cable, connect the signal generator output to the channel 1 input of the oscilloscope. Acquire the data 1 Test the upper bandwidth trigger sensitivity. a Set the signal generator to provide a 225 MHz signal with 70 mV rms amplitude. b Press the blue shift key, then press the Run key. Press the Trigger key.
Performance Test Record (logic analyzer) Performance Test Record (logic analyzer) HP 1660C/CS/CP-Series Logic Analyzer_______ Serial No.______________________ Recommended Test Interval - 2 Year/4000 hours Recommended next testing___________________ Test Settings Results Pass/Fail ________ Limits Measured TTL VL TTL VH ECL VL ECL VH -User VL - User VH + User VL + User VH 0 V User VL 0 V User VH +1.355 V +1.645 V -1.439 V -1.161 V -6.280 V -5.720 V +5.720 V +6.
Testing Performance Performance Test Record (logic analyzer) Performance Test Record (continued) Test Settings Results Limits Measured TTL VL TTL VH ECL VL ECL VH -User VL - User VH + User VL + User VH 0 V User VL 0 V User VH +1.355 V +1.645 V -1.439 V -1.161 V -6.280 V -5.720 V +5.720 V +6.280 V -100 mV +100 mV ________ ________ ________ ________ ________ ________ ________ ________ ________ ________ TTL VL TTL VH ECL VL ECL VH -User VL - User VH + User VL + User VH 0 V User VL 0 V User VH +1.
Testing Performance Performance Test Record (logic analyzer) Performance Test Record (continued) Test Settings Glitch Capture Minimum Detectable Glitch 3.
Testing Performance Performance Test Record (logic analyzer) Performance Test Record (continued) Test Settings Results Pass/Fail Single-Clock, Single-Edge Acquisition Pass/Fail All Pods, Channel 3 Setup/Hold Time 3.5/0.0 ns J↑ K↑ L↑ M↑ N↑ P↑ ________ ________ ________ ________ ________ ________ J↓ K↓ L↓ M↓ N↓ P↓ ________ _________ ________ ________ ________ ________ Setup/Hold Time 0.0/3.
Testing Performance Performance Test Record (logic analyzer) Performance Test Record (continued) Test Settings Results Enable pulse generator, channel 2 COMP (LED on) Multiple-Clock, Multiple-Edge Acquisition Disable pulse generator, channel 2 COMP (LED off) Pass/Fail Pass/Fail All Pods, Channel 3 Setup/Hold Time 4.5/0.0 ns J↑ + M↑ + N↑ K↑ + L↑ + P↑ ________ ________ J↓ + M↓ + N↓ K↓ + L↓ + P↓ ________ ________ Setup/Hold Time 0.0/4.
Testing Performance Performance Test Record (logic analyzer) Performance Test Record (continued) Test Settings Results Disable pulse generator, channel 1 COMP (LED off) Single-Clock, Multiple-Edge Acquisition Pass/Fail All Pods, Channel 3 Setup/Hold Time 4.0/0.0 ns J↕ K↕ L↕ M↕ N↕ P↕ _______ _______ _______ _______ _______ _______ Setup/Hold Time 0.0/4.0 ns J↕ K↕ L↕ M↕ N↕ P↕ _______ _______ _______ _______ _______ _______ Setup/Hold Time 2.0/2.
Performance Test Record (oscilloscope) Performance Test Record (oscilloscope) Test Settings Self-Tests DC CAL Output AC CAL Output Input Resistance Channel 1 Channel 2 5.000 Vdc ±10 mV 0.8 Vp_p ±10% 1.000 KHz ±10% Results Pass/Fail ________ Limits Measured 4.990 Vdc 5.010 Vdc ________ 0.72 Vp_p 0.
Testing Performance Performance Test Record (oscilloscope) Performance Test Record (oscilloscope) Test Settings Voltage Measurement Accuracy Results Limits Measured Channel 1 Zero Input -13.7 V to -14.3 V -3.43 V to -3.57 V -1.37 V to -1.43 V -137.0 mV to -143.0 mV 143.0 mV to 137.0 mV 1.43 V to 1.37 V 3.57 V to 3.43 V 14.3 V to 13.7 V ________ ________ ________ ________ ________ ________ ________ ________ Channel 2 Zero Input -13.7 V to -14.3 V -3.43 V to -3.57 V -1.37 V to -1.43 V -137.
Testing Performance Performance Test Record (oscilloscope) Performance Test Record (oscilloscope) Test Settings Results Bandwidth Limit Measured Channel 1 ≤−3.0 dB ________ Channel 2 ≤−3.0 dB ________ 5.500 ns ± 150 ps MEAN X-O ________ MIN X-O ________ MEAN X-O - MIN X-O ________ MAX X-O ________ MAX X-O - MEAN X-O ________ 99.
Performance Test Record (pattern generator) Performance Test Record (pattern generator) Test Settings Results Pass/Fail Self-Tests 3–104 ________
4 Logic analyzer calibration 4–2 To calibrate the oscilloscope 4–3 Set up the equipment 4–3 Load the Default Calibration Factors 4–4 Self Cal menu calibrations 4–5 To adjust the CRT monitor alignment 4–6 To adjust the CRT intensity 4–8 Calibrating and Adjusting
Calibrating and Adjusting This chapter gives you instructions for calibrating and adjusting the logic analyzer. Adjustments to the logic analyzer include adjusting the CRT monitor assembly. To periodically verify the performance of the analyzer, refer to "Testing Performance" in chapter 3. Logic analyzer calibration The logic analyzer circuitry of the HP 1660C-series, HP 1660CP-series, and HP 1660CS-series Logic Analyzers does not require an operational accuracy calibration.
To calibrate the oscilloscope Equipment Required Equipment Critical Specification Recommended Model/Part Qty Cable (2) BNC, 9-inch (equal length) HP 10502A 1 Cable BNC HP 10503A Adapter BNC tee (m)(f)(f) HP 1250-0781 Adapter BNC (f)(f) (ug-914/u) HP 1250-0080 1 Set up the equipment Turn on the logic analyzer. Let it warm up for 30 minutes if you have not already done so.
Calibrating and Adjusting To calibrate the oscilloscope Load the Default Calibration Factors 1 2 3 4 5 Note that once the default calibration factors are loaded, all calibrations must be done. This includes all of the calibrations in the Self Cal menu. The calibration must be performed in the exact sequence listed below. Press the System key. Select System, then select Scope. Select the menu field (top row, second from the left), then select Scope Calibration from the pop-up menu.
Calibrating and Adjusting To calibrate the oscilloscope Self Cal menu calibrations Messages will be displayed as each calibration routine is completed to indicate calibration has passed or failed. The resulting calibration factors are automatically stored to nonvolatile RAM at the conclusion of each calibration routine. The Self Cal menu lets you optimize vertical sensitivity (Vert Cal) for channels 1 and 2 individually or both channels on a board simultaneously.
To adjust the CRT monitor alignment This procedure must be performed by trained personnel. Adjustments are made with the cover removed and power applied. WARNING Do not touch the CRT monitor sweep board. High voltages exist on the sweep board that can cause personal injury. Equipment Required Equipment Critical Specification Recommended Model/Part Alignment Tool 1 8710-1300 1 Turn off the logic analyzer, then disconnect the power cord. Remove the cover.
Calibrating and Adjusting To adjust the CRT monitor alignment 4 Enter the Sys PV tests, then enter the Display Test. A grid pattern should appear. 5 If the display is tilted (rotated), adjust the CRT yoke by rotating it to straighten the display. You may need to loosen the screw on the yoke in order to rotate it. If so, ensure you tighten the screw after you have adjusted the yoke to the desired position. WARNING Do not touch the CRT monitor sweep board.
To adjust the CRT intensity This procedure must be performed by trained personnel. Adjustments are made with the cover removed and power applied. WARNING Do not touch the CRT monitor sweep board. High voltages exist on the sweep board that can cause personal injury. Equipment Required Equipment Critical Specification Recommended Model/Part Alignment Tool 1 8710-1300 Light Power Meter United Detector 351 1 Turn off the logic analyzer, then disconnect the power cord. Remove the cover.
Calibrating and Adjusting To adjust the CRT intensity WARNING Do not touch the CRT monitor sweep board. High voltages exist on the sweep board that can cause personal injury. 2 7 The light power meter should read 137-154 cd/m . If the measurement is out of this range, use the adjustment tool to adjust the Contrast potentiometer on the monitor driver board. 8 Press the front panel Select key. The display should show a half bright test screen.
4–10
5 To use the flowcharts 5–2 To check the power-up tests 5–17 To run the self-tests 5–18 To test the power supply voltages 5–24 To test the CRT monitor signals 5–26 To test the keyboard signals 5–27 To test the flexible disk drive voltages 5–28 To test the hard disk drive voltages 5–30 To perform the BNC test 5–31 To test the logic analyzer probe cables 5–32 To verify pattern output (HP 1660CP-Series only) 5–36 To test the auxiliary power 5–38 Troubleshooting
Troubleshooting This chapter helps you troubleshoot the logic analyzer to find defective assemblies. The troubleshooting consists of flowcharts, self-test instructions, and tests. This information is not intended for component-level repair. If you suspect a problem, start at the top of the first flowchart. During the troubleshooting instructions, the flowcharts will direct you to perform other tests. The service strategy for this instrument is the replacement of defective assemblies.
Troubleshooting To use the flowcharts Troubleshooting Flowchart 1 5–3
Troubleshooting To use the flowcharts Troubleshooting Flowchart 2 5–4
Troubleshooting To use the flowcharts Troubleshooting Flowchart 3 5–5
Troubleshooting To use the flowcharts Troubleshooting Flowchart 4 5–6
Troubleshooting To use the flowcharts Troubleshooting Flowchart 5 5–7
Troubleshooting To use the flowcharts Troubleshooting Flowchart 6 5–8
Troubleshooting To use the flowcharts Troubleshooting Flowchart 7 5–9
Troubleshooting To use the flowcharts Troubleshooting Flowchart 8 5–10
Troubleshooting To use the flowcharts Troubleshooting Flowchart 9 5–11
Troubleshooting To use the flowcharts Troubleshooting Flowchart 10 5–12
Troubleshooting To use the flowcharts Troubleshooting Flowchart 11 5–13
Troubleshooting To use the flowcharts Troubleshooting Flowchart 12 5–14
Troubleshooting To use the flowcharts Troubleshooting Flowchart 13 5–15
Troubleshooting To use the flowcharts Troubleshooting Flowchart 14 5–16
Troubleshooting To check the power-up tests To check the power-up tests The logic analyzer automatically performs power-up tests when you apply power to the instrument. The revision number of the operating system shows in the upper-right corner of the screen during these power-up tests. As each test completes, either "passed" or "failed" prints on the screen in front of the name of each test. 1 Disconnect all inputs, then insert a formatted disk into the flexible disk drive.
Troubleshooting To run the self-tests To run the self-tests Self-tests identify the correct operation of major functional areas of the instrument. You can run all self-tests without accessing the interior of the instrument. If a self-test fails, the troubleshooting flowcharts instruct you to change a part of the instrument. These procedures assume the files on the PV disk have been copied to the /SYSTEM subdirectory on the hard disk drive.
Troubleshooting To run the self-tests 5 Select ROM Test. The ROM Test screen is displayed. You can run all tests at one time by running All System Tests. To see more details about each test, you can run each test individually. This example shows how to run an individual test. 6 Select Run, then select Single. To run a test continuously, select Repetitive. Select Stop to halt a repetitive test. For a Single run, the test runs one time, and the screen shows the results.
Troubleshooting To run the self-tests 7 To exit the ROM Test, select Done. Note that the status changes to Passed or Failed. 8 Install a formatted disk that is not write protected into the flexible disk drive. Connect an RS-232-C loopback connector onto the RS-232-C port. Run the remaining System Tests in the same manner. 9 Select the Front Panel Test. A screen duplicating the front-panel appears on the screen. a Press each key on the front panel.
Troubleshooting To run the self-tests 11 Select Sys PV, then select Analy PV in the pop-up menu. Select Chip 2 Tests. You can run all the analyzer tests at one time by selecting All Analyzer Tests. To see more details about each test, you can run each test individually. This example shows how to run Chip 2 Tests. Chip 3, 4, and 5 Tests operate the same as Chip 2 Tests. 12 In the Chip 2 Tests menu, select Run, then select Single. The test runs one time, then the screen shows the results.
Troubleshooting To run the self-tests 13 Select Board Tests, then select Run. When the Board Tests are finished, select Done. 14 Select Data Input Inspection. All lines should show activity. Select Done to exit the Data Input Inspection. If you have an HP 1660C-series Logic Analyzer (no oscilloscope or pattern generator), go to step 19. If you have an HP 1660CP-series Logic Analyzer, go to step 18. If you have an HP 1660CS-series Logic Analyzer, continue with step 15.
Troubleshooting To run the self-tests 17 In the Data Memory Test menu, select Run, then select Single. The test runs one time, then the screen shows the results. When the test is finished, select Done. To run a test continuously, select Repetitive. Select Stop to halt a Repetitive Run. Go to step 19 to exit the test system. 18 For the HP 1660CP-series Logic Analyzers, Select Analy PV, then select Patt Gen in the pop-up menu. In the Patt Gen menu select Clock Source Test.
Troubleshooting To test the power supply voltages To test the power supply voltages To check the voltages, the power supply must be loaded by either the acquisition board or with an added resistor. Refer to chapter 6, "Replacing Assemblies," for instructions to remove or replace covers and assemblies. WARNING Hazard voltages exist on the power supply, the CRT, and the CRT driver board.
Troubleshooting To test the power supply voltages 6 Check for the voltages on the power supply cable using the values in the following table. Signals on the Power Supply Cable Pin Signal Pin Signal 1 +5.00 V 11 –5.20 V 2 +5.00 V 12 Ground 3 +5.00 V 13 +12 V 4 +5.00 V 14 Ground 5 Ground (Digital) 15 –12 V 6 Ground (Digital) 16 Ground 7 Ground (Digital) 17 +12 V (Display) 8 Ground (Display) 18 –5.20 V 9 +3.
Troubleshooting To test the CRT monitor signals To test the CRT monitor signals Refer to chapter 6, "Replacing Assemblies," for instructions to remove or replace covers and assemblies. WARNING Hazard voltages exist on the power supply, the CRT, and the CRT driver board. This procedure is to be performed by service-trained personnel aware of the hazards involved, such as fire and electrical shock. 1 Remove the cover of the instrument.
Troubleshooting To test the keyboard signals To test the keyboard signals Refer to chapter 6, "Replacing Assemblies," for instructions to remove covers and assemblies. WARNING Hazard voltages exist on the power supply, the CRT, and the CRT driver board. This procedure is to be performed by service-trained personnel aware of the hazards involved, such as fire and electrical shock. 1 Turn off the instrument and remove the power cable.
Troubleshooting To test the flexible disk drive voltages To test the flexible disk drive voltages Refer to chapter 6, "Replacing Assemblies," for instructions to remove or replace covers and assemblies. WARNING This procedure is to be performed by service-trained personnel aware of the hazards involved, such as fire and electrical shock.
Troubleshooting To test the flexible disk drive voltages 6 Check for the following voltages and signals using an oscilloscope.
Troubleshooting To test the hard disk drive voltages To test the hard disk drive voltages Refer to chapter 6, "Replacing Assemblies," for instructions to remove or replace covers and assemblies. This procedure is to be performed by service-trained personnel aware of the hazards involved, such as fire and electrical shock.
Troubleshooting To perform the BNC test The test will not immediately stop when Stop is selected; it will continue until the current iteration of the disk test is completed and then stop. 7 Disconnect the disk drive cables. Re-install the hard disk drive onto the disk drive assembly, and then re-install the disk drive assembly in the logic analyzer. 8 Reconnect the disk drive cables and install the cover on the logic analyzer.
Troubleshooting To test the logic analyzer probe cables To test the logic analyzer probe cables This test allows you to functionally verify the probe cable and probe tip assembly of any of the logic analyzer pods. Only one probe cable can be tested at a time. Repeat this test for each probe cable to be tested. Equipment Required Equipment Critical Specification Recommended Model/Part Pulse Generator 100 MHz, 3.
Troubleshooting To test the logic analyzer probe cables 4 Set up the Format menu. a Press the Format key. b Move the cursor to the field showing the channel assignments for the pod under test. Press the Clear Entry key until the pod channels are all assigned (all asterisks (*)). Press the Done key. c Select Master Clock, then select a double edge for the clock of the pod under test. Turn off the other clocks. d In the Master Clock menu, select Setup/Hold, then select 4.0/0.0 ns for the pod being tested.
Troubleshooting To test the logic analyzer probe cables e Select the field to the right of the pod being tested, then select TTL. 5 Set up the Trigger menu. a Press the Trigger key. b Select Modify Trigger, then select Clear Trigger, then select All. 6 Set up the Listing menu. a Press the List key. b Select the field to the right of Base, then select Binary.
Troubleshooting To test the logic analyzer probe cables 7 Using four 6-by-2 test connectors, four BNC Couplers, and four SMA (m) - BNC (f) Adapters, connect the logic analyzer to the pulse generator channel outputs. To make the test connectors, see chapter 3, "Testing Performance." a Connect the even-numbered channels of the lower byte of the pod under test to the pulse generator channel 1 Output and J-clock.
Troubleshooting To verify pattern output (HP 1660CP-Series only) To verify pattern output (HP 1660CP-Series only) Equipment Required Equipment Critical Specification Recommended Model/Part Oscilloscope ≥ 500 MHz Bandwidth HP 54522A Probe 500 MHz Bandwidth HP 10441A Output Data Pod no substitute 10460A - series 1 Connect one of the 10460-series data pods to the end of the pattern generator Pod 1 cable. 2 Touch Output Patterns. In the pop-up menu, touch Checkerboard Pattern.
Troubleshooting To verify pattern output (HP 1660CP-Series only) 4 Repeat step 3 for each of the remaining four data pods. 5 Connect one of the 10460-series clock pods to the end of the pattern generator clock cable. 6 Using the oscilloscope as in step 3, verify the existence of logic-level transitions by touching the oscilloscope probe to each clock output of the clock pod. 7 In the pattern generator Output Patterns menu, touch Stop, then touch Done to exit the menu.
Troubleshooting To test the auxiliary power To test the auxiliary power The +5 V auxiliary power is protected by a current overload protection device. If the current on pins 1 and 39 exceed 0.33 amps, the circuit will open. When the short is removed, the circuit will reset in approximately 1 minute. There should be +5 V after the 1 minute reset time. Equipment Required Equipment Critical Specifications Recommended Model/Part Digital Multimeter 0.1 mV resolution, better than HP 3478A 0.
6 To remove and replace the Handle 6–5 Feet and tilt stand 6–5 Cover 6–5 Disk drive assembly 6–6 Power supply 6–7 CPU board 6–7 SIMM memory 6–8 Switch actuator assembly 6–9 Rear panel assembly 6–10 HP 1660C-series acquisition board 6–11 HP 1660CS-series oscilloscope board 6–12 HP 1660CP-series pattern generator board 6–13 Front panel and keyboard 6–14 Intensity adjustment 6–14 Monitor 6–15 Handle plate 6–15 Fan 6–16 Line filter 6–16 HP 1660CP-series pattern generator cables 6–17 HP-IB and RS-232-C cables 6
Replacing Assemblies This chapter contains the instructions for removing and replacing the assemblies of the logic analyzer. Also in this chapter are instructions for returning assemblies. WARNING CAUTION Hazardous voltages exist on the power supply, the CRT, and the CRT driver board. To avoid electrical shock, disconnect the power from the instrument before performing the following procedures.
Replacing Assemblies Exploded View Listing A1 A2 A3 A4 A5 Keyboard CPU board I/O Board Acquisition board Oscilloscope board * MP1 MP2 MP3 MP4 MP5 Intensity adjustment Disk drive bracket Fan guard Rear panel Line filter W1 W2 W3 W4 W5 HP-IB cable Fan cable RS-232-C cable Flexible disk drive cable Cable-60 conductor A5 A6 A7 A9 A10 A11 A12 Pattern Generator board* Attenuator ** Switch actuator Power supply Hard disk drive Flexible disk drive SIMM MP6 MP7 MP8 MP11 MP19 MP20 MP23 Ground bracket Ground
Replacing Assemblies Exploded View of the HP 1660C 6–4
Replacing Assemblies To remove and replace the handle To remove and replace the handle • Remove the two screws in the endcaps, then lift off the handle. To remove and replace the feet and tilt stand Remove the screws connecting the four rear feet to the instrument. Separate the rear feet from the instrument to remove them. Press the locking tab on the bottom feet, then remove them. Remove the tilt stand from the bottom front feet by lifting the stand up and out of the foot.
Replacing Assemblies To remove and replace the disk drive assembly To remove and replace the disk drive assembly 1 Using previous procedures, remove the following assemblies: • Handle • Rear Feet • Cover 2 Disconnect the two disk drive ribbon cables from the rear of both disk drives. Peel 3 4 5 6 7 8 the cables away from the double-sided tape used to secure the cables to the disk drive bracket. Disconnect the power cable from the rear of the hard disk drive.
Replacing Assemblies To remove and replace the power supply To remove and replace the power supply 1 Using previous procedures, remove the following assemblies: • • • • Handle Rear Feet Cover Disk Drive Assembly Hazardous voltages exist on the power supply. To avoid electrical shock, disconnect the power from the instrument before performing the following procedures. After disconnecting the power, wait at least three minutes for the capacitors to discharge before continuing.
Replacing Assemblies To remove and replace SIMM memory To remove and replace SIMM memory 1 Using previous procedures, remove the following assemblies: • • • • • • WARNING Handle Rear Feet Cover Disk Drive Assembly Power Supply CPU Board Hazardous voltages exist on the power supply. To avoid electrical shock, disconnect the power from the instrument before performing the following procedures.
Replacing Assemblies To remove and replace the switch actuator assembly To remove and replace the switch actuator assembly 1 Using previous procedures, remove the following assemblies: • • • • • • Handle Rear Feet Cover Disk Drive Assembly Power Supply CPU Board 2 Make sure the power switch is in the off position. 3 Disconnect the switch actuator from the line filter. a Slide the clamp off of the outer casing far enough to release the switch actuator assembly.
Replacing Assemblies To remove and replace the rear panel assembly To remove and replace the rear panel assembly 1 Using previous procedures, remove the following assemblies: • • • • • Handle Rear Feet Cover Disk Drive Assembly Power Supply 2 Remove the switch actuator cable from the line filter according to "To remove and replace the switch actuator assembly." 3 Disconnect the BNC In/Out and fan cables on the acquisition board. 4 Disconnect the RS-232-C and HP-IB cables from the CPU board.
Replacing Assemblies To remove and replace the HP 1660C-series acquisition board To remove and replace the HP 1660C-series acquisition board 1 Using previous procedures, remove the following assemblies: • • • • • • Handle Rear Feet Cover Rear Panel Disk Drive Assembly Power Supply 2 Disconnect the sweep cable from acquisition board. 3 Disconnect the CPU board interface cable by pressing down on the cable release tabs on the cable socket located on the board. 4 Disconnect the power supply cable.
Replacing Assemblies To remove and replace the HP 1660CS-series oscilloscope board To remove and replace the HP 1660CS-series oscilloscope board 1 Using previous procedures, remove the following assemblies: • • • • • • Handle Rear Feet Cover Rear Panel Disk Drive Assembly Power Supply 2 Disconnect the sweep cable from acquisition board. 3 Disconnect the CPU board interface cable by pressing down on the cable release tabs on the cable socket located on the board. 4 Disconnect the power supply cable.
Replacing Assemblies To remove and replace the HP 1660CP-series pattern generator board To remove and replace the HP 1660CP-series pattern generator board 1 Using previous procedures, remove the following assemblies: • • • • • • Handle Rear Feet Cover Rear Panel Disk Drive Assembly Power Supply 2 Disconnect the sweep cable from acquisition board. 3 Disconnect the CPU board interface cable by pressing down on the cable release tabs on the cable socket located on the board.
Replacing Assemblies To remove and replace the front panel and keyboard To remove and replace the front panel and keyboard 1 Using previous procedures, remove the following assemblies: • • • • • • Handle Rear Feet Cover Disk Drive Assembly Power Supply CPU Board 2 Remove the four screws connecting the front panel. 3 Slide the front panel assembly out the front of the instrument. 4 Slide the spacers out the front of the instrument to remove them.
Replacing Assemblies To remove and replace the monitor To remove and replace the monitor 1 Using previous procedures, remove the following assemblies: • • • • • • • • • • • Handle Rear Feet Cover Disk Drive Assembly Power Supply CPU Board Rear Panel Acquisition Board Oscilloscope Board (HP 1660CS-series only) Pattern Generator Board (HP 1660CP-series only) Intensity Adjustment Hazardous voltages exist on the CRT and the CRT driver board.
Replacing Assemblies To remove and replace the fan To remove and replace the fan 1 Using previous procedures, remove the following assemblies: • • • • • • 2 3 4 5 Handle Rear Feet Cover Disk Drive Assembly Power Supply Rear Panel Remove the four fan screws. Lift the fan away from the rear panel. Lift the fan guard away from the rear panel. Reverse this procedure to install the fan. When installing the fan, verify the correct orientation of the fan.
Replacing Assemblies To remove and replace the HP 1660CP-series pattern generator cables To remove and replace the HP 1660CP-series pattern generator cables 1 Using previous procedures, remove the following assemblies: • • • • • • Handle Rear Feet Cover Disk Drive Assembly Power Supply CPU Board 2 Remove the two screws securing the pattern generator cable clamp to the rear panel and remove the cable clamp.
Replacing Assemblies To remove and replace the I/O board To remove and replace the I/O board 1 Using previous procedures, remove the following assemblies: • • • • • • Handle Rear Feet Cover Disk Drive Assembly Power Supply Rear Panel 2 Remove the two jackscrews that attach the parallel printer (Centronics) port to the rear panel. 3 Remove four screws that secure the I/O board to the rear panel.
7 Replaceable Parts Ordering 7–2 Replaceable Parts List 7–3 Exploded View 7–4 Power Cables and Plug Configurations 7–8 Replaceable Parts
Replaceable Parts This chapter contains information for identifying and ordering replaceable parts for your logic analyzer. Replaceable Parts Ordering Parts listed To order a part on the list of replaceable parts, quote the Hewlett-Packard part number, indicate the quantity desired, and address the order to the nearest Hewlett-Packard Sales Office.
Replaceable Parts Replaceable Parts List Replaceable Parts List The replaceable parts list is organized by reference designation and shows exchange assemblies, electrical assemblies, then other parts. The exploded view does not show all of the parts in the replaceable parts list.
Replaceable Parts Exploded View Exploded View Exploded view of the HP 1660 logic analyzer.
Replaceable Parts Exploded View HP 1660 Series Replaceable Parts Ref. Des.
Replaceable Parts Exploded View HP 1660 Series Replaceable Parts Ref. Des. HP Part Number QTY Description H13 H14 H15 H16 H17 0515-1103 0515-0664 2950-0072 2950-0001 0535-0056 2 4 1 2 3 MSFH M3 10 T10 (trim strip cover to cabinet) MSPH M3 12 SMS10 (rear feet to cabinet) NUTH 1/4-32 .062 (intensity adjustment) NUTH 3/8-32 .093 (BNC trigger ports) NUT-HEX (monitor assembly) H20 H21 H22 0515-0382 0515-1349 0380-1482 3 4 2 SM assembly M4 X 0.7 12MM-LG (monitor assembly, handle) SM M3 X 0.
Replaceable Parts Exploded View HP 1660 Series Replaceable Parts Ref. Des.
Replaceable Parts Power Cables and Plug Configurations Power Cables and Plug Configurations This instrument is equipped with a three-wire power cable. The type of power cable plug shipped with the instrument depends on the country of destination. The W15 reference designators (table, previous page) show option numbers of available power cables and plug configurations.
8 Block-Level Theory 8–3 The HP 1660C/CS/CP Series Logic Analyzer 8–3 The Logic Acquisition Board 8–7 The Oscilloscope Board 8–10 The Pattern Generator Board 8–13 Self-Tests Description 8–15 Power-up Self-Tests 8–15 System Tests (System PV) 8–16 Analyzer Tests (Analy PV) 8–20 Oscilloscope tests (Scope PV) 8–22 Pattern Generator tests (Patt Gen) 8–23 HP-IB 8–27 RS-232-C 8–28 Theory of Operation
Theory of Operation This chapter tells the theory of operation for the logic analyzer and describes the self-tests. The information in this chapter is to help you understand how the logic analyzer operates and what the self-tests are testing. This information is not intended for component-level repair.
Block-Level Theory The block-level theory is divided into two parts: theory for the logic analyzer and theory for the acquisition boards. A block diagram is shown with each theory.
Theory of Operation The HP 1660C/CS/CP Series Logic Analyzer HP 1660C/CS/CP Series Theory CPU Board The microprocessor is a Motorola 68EC020 running at 25 MHz. The microprocessor controls all of the functions of the logic analyzer including processing and storing data, displaying data, and configuring the acquisition ICs to obtain and store data. System Memory The system memory is made up of both read-only memory (ROM) and random access memory (RAM). Two types of ROM are used.
Theory of Operation The HP 1660C/CS/CP Series Logic Analyzer HP-IB Interface The instrument interfaces to HP-IB as defined by IEEE Standard 488.2. The interface consists of an HP-IB controller and two octal drivers/receivers. The microprocessor routes HP-IB data to the controller. The controller then buffers the 8-bit HP-IB data bits and generates the bus handshaking signals. The data and handshaking signals are then routed to the HP-IB bus through the octal line drivers/receivers.
Theory of Operation The HP 1660C/CS/CP Series Logic Analyzer Keyboard/Mouse Interface An 82C42PC PS2 controller makes up the PS2 Keyboard/Mouse interface. The PS2 controller interfaces the logic analyzer backplane with the keyboard and/or mouse devices. I/O Board The Input/Output (I/O) Board primarily includes a Centronics port and two mini-DIN (PS/2) ports for the HP 1660C/CS/CP-series products.
Theory of Operation The Logic Acquisition Board The Logic Acquisition Board The Logic Acquisition Board 8–7
Theory of Operation The Logic Acquisition Board Logic Acquisition Board Theory Probing The probing circuit includes the probe cable and terminations. The probe cable consists of two 17-channel pods which are connected to the circuit board using a high-density connector. Sixteen single-ended data channels and one single-ended clock/data channel are passed to the circuit board per pod. If the clock/data channel is not used as a state clock in state acquisition mode, it is available as a data channel.
Theory of Operation The Logic Acquisition Board Clock optimization involves using programmable delays on board the IC to position the master clock transition where valid data is captured. This procedure greatly reduces the effects of channel-to-channel skew and other propagation delays. In the timing acquisition mode, an oscillator-driven clock circuit provides a four-phase, 100-MHz clock signal to each of the acquisition ICs.
Theory of Operation The Oscilloscope Board The Oscilloscope Board The Oscilloscope Board 8–10
Theory of Operation The Oscilloscope Board Oscilloscope Board Theory (HP 1660CS series only) Attenuator/Preamp Theory of Operation The channel signals are conditioned by the attenuator/preamps, thick film hybrids containing passive attenuators, impedance converters, and a programmable amplifier. The channel sensitivity defaults to the standard 1-2-4 sequence (other sensitivities can be set also).
Theory of Operation The Oscilloscope Board Time Base The time base provides the sample clocks and timing necessary for data acquisition. It consists of the 100 MHz reference oscillator and time base hybrid. The 100 MHz reference oscillator provides the base sample frequency. The time base hybrid has programmable dividers to provide the rest of the sample frequencies appropriate for the time range selected.
Theory of Operation The Pattern Generator Board The Pattern Generator Board The Pattern Generator Board Pattern Generator Board Theory (HP 1660CP series only) Loop Register The loop register holds the programmable vector flow information. When the pattern generator reaches the end of the vector listing, the loop register is queried for the RAM address location of the next user-programmed vector. In many cases, the next vector address location would be the start of the vector listing.
Theory of Operation The Pattern Generator Board Output Driver The output driver circuit is made up of a series of latch/logic translators and multiplexers. The latch/translators convert the working-level TTL signals to output-level ECL signals for each channel. The ECL-level signals are then directed to the multiplexers. The multiplexers, one per channel, direct the programmed data patterns to the output channels.
Self-Tests Description The self-tests identify the correct operation of major functional areas in the logic analyzer. The self-tests are not intended for component-level diagnostics. Three types of tests are performed on the HP 1660C/CS/CP series logic analyzers: the power-up self-tests, the functional performance verification self-tests, and the parametric performance verification tests. The power-up self-tests are performed when power is applied to the instrument.
Theory of Operation System Tests (System PV) RAM Test The RAM test checks the video RAM (VRAM), system dynamic RAM (DRAM), and static RAM memory within the real time clock IC. The microprocessor first performs a write/read in each memory location of the VRAM. At each VRAM memory location a test pattern is written, read, and compared. An inverse test pattern is then written, read, and compared.
Theory of Operation System Tests (System PV) HP-IB Test The HP-IB test performs a write/read operation to each of the registers of the HP-IB IC. A test pattern is written to each register in the HP-IB IC. The pattern is then read and compared with a known value. Passing the HP-IB test implies that the read/write registers in the HP-IB IC can store a logical "1" or a logical "0," and that the HP-IB IC is functioning properly. Incoming and outgoing HP-IB information will not be corrupted by the HP-IB IC.
Theory of Operation System Tests (System PV) Perform Test All Selecting Perform Test All will initiate all of the previous functional verification tests in the order they are listed. The failure of any or all of the tests will be reported in the test menu field of each of the tests. The Perform All Test will not initiate the Front Panel Test or the Display Test. Front Panel Test A mock-up of the logic analyzer front panel is displayed on the CRT when the Front Panel Test is initiated.
Theory of Operation System Tests (System PV) Status Bits Bit 0 The internal registers of the LAN IC are loaded with known test values and then are read. If this bit is not set, it implies that the LAN IC is operating properly and that the microprocessor can communicate with the LAN IC. If this bit is set, then the LAN module is not operational and must be replaced.
Theory of Operation Analyzer Tests (Analy PV) Analyzer Tests (Analy PV) The analyzer tests are functional performance verification tests. There are three types of analyzer tests: the Board Test, the Chip Tests, and the Data Input Inspection. The following describes the analyzer self-tests: Board Test The Board Test functionally verifies the two oscillators and the 9-channel comparators on the circuit board. First, the oscillators are checked using the event counter on one of the acquisition ICs.
Theory of Operation Analyzer Tests (Analy PV) Resource Test The pattern, range, edge, and glitch recognizers are tested and verified. First, the test register is verified for correct operation. Next, the pattern comparators are tested to ensure that each bit in the recognizer memory location as well as the logic driver/receiver are operating. The edge and glitch pattern detectors are then verified in a similar manner.
Theory of Operation Oscilloscope tests (Scope PV) Oscilloscope tests (Scope PV) The following self-tests check the major components of the HP 1660CS-series oscilloscope board as well as all associated circuitry. When the self-tests have all been completed with a "PASS" status, the major data and control pipelines in the HP 1660CS-series oscilloscope board are functioning properly. Data Memory Test This test verifies the correct operation of the FISO (fast-in/slow-out) data memory on the board.
Theory of Operation Pattern Generator tests (Patt Gen) Pattern Generator tests (Patt Gen) The following section contains a description of each of the the pattern generator self tests. Clock Source Test The Clock Source Test checks that the internal clock sources are functioning by verifying the presence of a given clock source. The test toggles each clock source in the following fashion. First the board is stopped and outputs are disabled.
Theory of Operation Pattern Generator tests (Patt Gen) Bits 6-13 contain the row of the page that failed. Bits 0-5 contain the failure code for the six RAM ICs on the board. Bits 0-4 contain the failure code for the RAMs for pod 1-5, and bit 5 contains the failure code for the RAM used for instructions. A one in the bit position indicates that that RAM provided incorrect information.
Theory of Operation Pattern Generator tests (Patt Gen) Diagnostic Integer Value: This test is only valid for signals on the master board of the configuration. The values returned from any expansion cards will be zero.
Theory of Operation Pattern Generator tests (Patt Gen) Subtest #3 — If Instruction Test This test checks the functionality of the if branching. Instruction memory is loaded with a wait on event ’a’ instruction in the non-if branch of memory and a break instruction in the if branch. The first pass of the test sets the branch pattern to a never branch condition. The board is started and a wait is begun for the vectors to get to the wait instruction.
HP-IB The Hewlett-Packard Interface bus (HP-IB) is Hewlett-Packard’s implementation of IEEE Standard 488-1978, "Standard Digital Interface for Programming Instrumentation." HP-IB is a carefully defined interface that simplifies the integration of various instruments and computers into systems. The interface makes it possible to transfer messages between two or more HP-IB compatible devices. HP-IB is a parallel bus of 16 active signal lines divided into three functional groups according to function.
RS-232-C The logic analyzer interfaces with RS-232-C communication lines through a standard 25 pin D connector. The logic analyzer is compatible with RS-232-C protocol. When a hardwire handshake method is used, the Data Terminal Ready (DTR) line, pin 20 on the connector, is used to signal if space is available for more data in the logical I/O buffer. Pin outs of the RS-232-C connectors are listed in the following table.
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Product Warranty This Hewlett-Packard product has a warranty against defects in material and workmanship for a period of one year from date of shipment. During the warranty period, Hewlett-Packard Company will, at its option, either repair or replace products that prove to be defective. For warranty service or repair, this product must be returned to a service facility designated by Hewlett-Packard.
