FuturePlus® Systems Corporation FBDIMM INTERPOSER PROBE FS2343 Users Manual For use with Agilent Technologies Logic Analyzers Revision 1.
How to reach us.......................................................................................................................4 Product Warranty....................................................................................................................5 Limitation of warranty................................................................................................................... 5 Exclusive Remedies ...................................................................................
Symbols..................................................................................................................................17 Preferences ............................................................................................................................19 SM (SMBus) Control ............................................................................................................21 Paddle card Settings ..................................................................................
How to reach us For Technical Support: FuturePlus Systems Corporation 36 Olde English Road Bedford NH 03110 TEL: 603-471-2734 FAX: 603-471-2738 On the web http://www.futureplus.com For Sales and Marketing Support: FuturePlus Systems Corporation TEL: 719-278-3540 FAX: 719-278-9586 On the web http://www.futureplus.com FuturePlus Systems has technical sales representatives in several major countries. For an up to date listing please see http://www.futureplus.com/contact.html.
Product Warranty Due to wide variety of possible customer target implementations, the FS2343 FBDIMM Interposer probe has a 30 day acceptance period by the customer from the date of receipt. If the customer does not contact FuturePlus Systems within 30 days of the receipt of the product it will be determined that the customer has accepted the product. If the customer is not satisfied with the FS2343 FBDIMM Interposer probe they may return it within 30 days for a refund.
Software License Agreement IMPORTANT - Please read this license agreement carefully before opening the media envelope. Rights in the software are offered only on the condition that the customer agrees to all terms and conditions of the license agreement. Opening the media envelope indicates your acceptance of these terms and conditions. If you do not agree to the licensing agreement, you may return the unopened package for a full refund.
Introduction Thank you for purchasing the FuturePlus Systems FS2343 FBDIMM Interposer Logic Analyzer Probe. We think you will find the FS2343, along with your Agilent Technologies Logic Analyzer, a valuable tool for helping to characterize and debug your FBDIMMbased systems. This Users Guide will provide the information you need to install, configure, and use the FBDIMM Interposer Probe. If you have any questions about this Guide or use of this probe, please contact FuturePlus Systems Corporation.
FS2343 Probe Description The FS2343 FBDIMM Interposer Probe is based on the “Logic Analyzer Interface (LAI) Mode” of the Advanced Memory Buffer chip used on Fully Buffered DIMMs. This mode allows decoding of the Primary Southbound (from memory controller to FBDIMMs) Commands and Data as well as Secondary Northbound Commands and Data from the interposed FBDIMM located in the card edge connector on the top of the FS2343 Interposer Probe.
Probe Technical Feature Summary • • • • Quick and easy connection between a 240 pin FBDIMM connector and Agilent 1690x Logic Analyzers. Complete and accurate state analysis of Primary South and Secondary Northbound FBDIMM traffic as seen by the AMB in LAI mode on the Interposer probe. Integrated control of Advanced Memory Buffer Logic Analyzer Interface functions. Ability to accept an FBDIMM and hence allow full backplane performance evaluation.
Probe Set-up Probe overview The FS2343 Interposer probe uses an AMB device in “LAI” mode and provides the appropriate FBDIMM connections to an “interposed” FBDIMM device for it to operate within the memory bus. The LAI mode performs 2 functions. First, it demultiplexes and decodes the NB and SB traffic into the frame based information that is presented to the logic analyzer. Second, it acts as a link in the NB and SB chain in the memory bus.
The other orientation for the probe is with a 90 degree bend to either it’s front (AMB) or back side. There are right angle brackets provided to keep the probe in this position along with the associated nylon hardware. It is our recommendation that the interposed FBDIMM be placed in the probe before the probe is bent over. This provides additional stiffness at the FBDIMM straddle mount connector on the top of the probe.
Signal Assignments on Probe Pods There are signal connections for up to 6 different logic analyzer adapter cables (E5378A). This provides the user with some flexibility in terms of which signals they connect to based on the type of analysis that is needed, e.g. SB or NB only, all trigger events, SB and NB traffic together, etc. The 16753/4/5/6 cards require the E5378A adapter cables. 1 Adapter cable is required for 2 logic analyzer pods.
FBDIMM Paddle Board Connector layout Software Requirements For state analysis you must have version A.02.99.00 or later Agilent OS installed on the 1690x frame. Version A.02.99.00 contains the capability for SMBus control of the probe through the 16753/4/5/6 or 16950 cards. Setting up the 169xx Analyzer A CD containing the 16900 software is included in the FS2343 package.
This is what the FS2343 probe user should use to guide them in connecting adapter cables to analyzer card pods. If the pod connections need to be changed, it can be done using the Edit Probes feature, which is shown below. The Reference Designator field should be J9 through J15 from the paddle card. The next step is to select on the right hand side of the screen the 2 pods (Odd and Even) to connect to the analyzer cards. The drop box will show available pod connections.
Configuration File Labels The configuration files provided with the probe software have a number of labels defined that are useful in providing rapid identification of sampling position, DRAM, and Channel Command activity in the state listing. They can also be used as triggers for the logic analyzer.
TID – single Transaction identifier bit, used in Write Config. Register Channel Command. SD - Status delay, 2 bit field used in Sync command. Allows return status data to be delayed by up to 3 frames. EL0s - The EL0s bit indicates the channel should transition from the L0 state to the L0s state for exactly 42 frames. The L0 state is the state when the channel is ready to accept Channel and DRAM commands. The L0s state is an optional state used in systems that use power management.
Symbols Terms used in the FBDIMM protocol are defined under labels that are referred to as symbols. Symbols can be used in defining triggers or for use in default store qualifications. Below is a list of labels with the symbols defined. When using a label for which symbols are defined, change the hex property to sym to display the symbol representation. A, B and C below refer to the command slot A, B, C respectively in the southbound frame.
Channel Commands - A, B, C labels Symbol Symbol Value Channel NOP 0000 000x Sync 00000 001x Soft Channel Reset 0000 010x reserved 0000 011x Read Config Reg 0000 100x Write Config Reg 0000 101x DRAM CKE per Rank 0000 110x DRAM CKE per DIMM 0000 111x reserved2 0001 0xxx reserved3 0001 10xx Debug Exposed 0001 110x Debug Relative 0001 1110 Debug In-Band 0001 1111 Frame Type label Symbol Symbol Value command 00 Reserved 01 Command + Wdata 1x The DRAM commands A, B, C labels ar
Example using symbol “Activate” in a trigger Preferences The Preferences option is used to set the protocol decoder for failover mode. If the Southbound or Northbound is in failover mode, the preferences must be set accordingly. If the Northbound side is in failover the user must select which lane has failed in order for the decoder to decode the bus properly. The default settings for both the Northbound and Southbound are set to None, meaning they are both running at full potential.
Below is a picture of the preference options 20
SM (SMBus) Control Paddle card Settings The FS2343 probe is designed so that AMB/LAI device control can be either from the 16900 logic analyzer and the Probe Control application software resident there, or from another FS2343 probe (slave mode). This feature is controlled by means of a 6 position switch on the probe paddle card near the logic analyzer connections. The factory configuration is for 16900 control of the probe. The settings on the switch are dependent on the configuration file used.
Event Bus Cabling The Event Bus bits, Evbus[0:3], from other probes can be daisy chained across multiple probes in order to provide cross probe control of other probes. There are 2 EV cable connectors on each probe and both connectors are wired in parallel so that either can be used. Additionally, the probe has termination sensing circuitry so that the Evbus[0:3] signals are properly terminated on the probe if the cables are not used.
Setup The Set-up screen provides control over basic probe use. • The probe Configuration setup button allows the user to select when they want to set up the parameters within the AMB. The choices are always after link training, before link training only when needed, or always before link training. If all you are interested in is data after link training then leave always after link training selected.
SB Commands This allows Match or Mask control over any 3 Command patterns entered by the user in either hex or binary format. Furthermore, each of 3 patterns can be searched for in either Command Slot A, B or C, or all three patterns in all 3 Command Slots. The mask and match feature allows the user to set 3 different command patterns along with data to mask out. The user can then specify 3 events, which allows a user to specify a frame containing 3 command values to be passed to the logic analyzer.
Store Qualification This section controls the operation of the Qual Flag, Qual Stop Delay, and Qual Period Delay. It allows the user to select from 32 different events for the definition of Qual Start and Qual Stop. These settings control the state of the Store_qual flag for non-filtered frames. The Store_qual flag in the configuration file can then be used for trigger events, default storing, etc.
Trigger Events This capability allows the Probe user to define each of the AMB’s logic analyzer Triggers [0:10] to be set to one of 32 different event conditions seen by the AMB. It is important to note that not all LAITrig[0:10] signals are available to the logic analyzer. This is dependent on the configuration file loaded and the pod connections made to the logic analyzer.
Event Bus This feature controls the operation of the Event Bus signals EV[0:3] which can be used for communication and triggering between probes in an FBDIMM Channel.
State Analysis Operation For proper state analysis the user must choose the correct configuration file to load depending on what type of analysis is desired, such as analyzing both Northbound and Southbound activity or just one direction. The list of configuration files provided is on page 12.
After the probe has been configured, the trigger for the analyzer must be set. To set the trigger for the analyzer go to the setup menu bar and select “Advanced Trigger”. On the next window that pops up specify what you want the analyzer to trigger on. After you set the trigger, depress the run button (green arrow at the top of the screen on the overview, listing or waveform windows), the analyzer should be waiting for a trigger to occur at this point.
State Display Offline Analysis Offline analysis allows a user to be able to analyze a trace offline at a PC so it frees up the analyzer for another person to use the analyzer to capture data. If you have already used the FBDIMM Protocol Decoder license that was included with your package on a 1680/90/900 analyzer and would like to have the offline analysis feature on a PC you may buy additional licenses, please contact FuturePlus Sales department.
For data from a 16900 analyzer, open the .ala file using the File, Open menu selections and browse to the desired .ala file. After clicking “next” you must browse for the fast binary data file you want to import. Once you have located the file and clicked start import, the data should appear in the listing. After the data has been imported you must load the protocol decoder before you will see any decoding.
After the decoder has loaded, select Preferences from the overview screen and set the preferences to their correct value in order to decode the trace properly.
Appendix FS2343 Paddle Signal to Logic Analyzer Connector and Channel Mapping The following table shows how the FS2343 Probe connects FBDIMM AMB signals to the logic analyzer pods and channels through the 100 pin Samtec connectors. Note that the configuration files described earlier use various combinations of these Pod connections.
Signal name/Logical Signal Name NB_L4_B5_11 NB_L3_B5_11 NB_L6_B1_7 NB_L4_B2_8 NB_L3_B4_10 NB_L4_B1_7 NB_L4_B0_6 NB_L2_B3_9 GND Logic Analyzer channel number Signal Name/Logical Signal name 44 Even D9 NB_L7_B4_10 45 46 Ground Odd D10 47 48 Even D10 Ground 49 50 Ground Odd 11 51 52 Even D11 Ground 53 54 Ground Odd D12 55 56 Even D12 Ground 57 58 Ground Odd D13 59 60 Even D13 Ground 61 62 Ground Odd D14 63 64 Even D14 Ground 65 66 Ground Odd D15 67 68
J11 Pods 1(Odd) and 2 (Even) Signal name/Logical Signal Name SDA NB_L8_B5_11 NB_L10_B1_7 NB_L10_B2_8 NB_L5_B2_8 NB_L6_B3_9 NB_L11_B3_9 NB_L5_B0_6 NB_L11_B4_10 NB_L5_B5_11 NB_L4_B3_9 NB_L6_B5_11 NB_L6_B0_6 NB_L8_B2_8 Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Ground 1 2 Ground SM 3 4 SM Ground 5 6 Ground Odd D0 7 8 Even D0 Ground 9 10 Ground Odd D1 11 12 Even D1 Ground 13 14 Ground Odd D2 15 16 Even D2 Ground 17 18 Ground Odd D3 1
Signal name/Logical Signal Name SAMTEC Pin number SAMTEC Pin number Odd D13 59 60 Even D13 Ground 61 62 Ground Odd D14 63 64 Even D14 Ground 65 66 Ground Odd D15 67 68 Even D15 Ground 69 70 Ground NC 71 72 NC Ground 73 74 Ground NC 75 76 NC Ground 77 78 Ground NB_L11_B5_11 Odd D16P/Odd CLK 79 80 Even DP16P/Even CLK Ground 81 82 Ground GND Odd DP16N/Odd CLKN 83 84 Even DP16N/Even CLKN Ground 85 86 Ground Odd External Ref 87 88 Even External Ref
J15 Pod 1(Odd) Signal name/Logical Signal Name NB_L12_B1_7 NB_L7_B3_9 NB_L7_B1_7 NB_L7_B2_8 NB_L6_B4_10 NB_L9_B1_7 NB_L12_B2_8 NB_L12_B3_9 NB_L12_B5_11 NB_L12_B4_10 NB_L12_B0_6 NB_L10_B0_6 NB_L9_B4_10 TRIGGER0 Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Ground 1 2 Ground NC 3 4 NC Ground 5 6 Ground Odd D0 7 8 Even D0 Ground 9 10 Ground Odd D1 11 12 Even D1 Ground 13 14 Ground Odd D2 15 16 Even D2 Ground 17 18 Ground Odd D3 19 20
Signal name/Logical Signal Name TRIGGER1 TRIGGER2 Anly_clkp Anly_clkn Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Odd D14 63 64 Even D14 Ground 65 66 Ground Odd D15 67 68 Even D15 Ground 69 70 Ground NC 71 72 NC Ground 73 74 Ground NC 75 76 NC Ground 77 78 Ground Odd D16P/Odd CLK 79 80 Even DP16P/Even CLK Ground 81 82 Ground Odd DP16N/Odd CLKN 83 84 Even DP16N/Even CLKN Ground 85 86 Ground Odd Externa
J12 Pods 1(Odd) and 2 (Even) Signal name/Logical Signal Name NB_L13_B2_8 NB_L7_B3_9 NB_L7_B1_7 NB_L7_B2_8 NB_L6_B4_10 NB_L9_B1_7 NB_L13_B4_10 NB_L13_B3_9 NB_L13_B0_6 NB_L13_B1_7 NB_L13_B5_11 NB_L10_B0_6 NB_L9_B4_10 TRIGGER0 Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Ground 1 2 Ground NC 3 4 NC Ground 5 6 Ground Odd D0 7 8 Even D0 Ground 9 10 Ground Odd D1 11 12 Even D1 Ground 13 14 Ground Odd D2 15 16 Even D2 Ground 17 18 Ground Od
Signal name/Logical Signal Name TRIGGER1 TRIGGER2 TRIGGER4 GND Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Ground 61 62 Ground Odd D14 63 64 Even D14 Ground 65 66 Ground Odd D15 67 68 Even D15 Ground 69 70 Ground NC 71 72 NC Ground 73 74 Ground NC 75 76 NC Ground 77 78 Ground Odd D16P/Odd CLK 79 80 Even DP16P/Even CLK Ground 81 82 Ground Odd DP16N/Odd CLKN 83 84 Even DP16N/Even CLKN Ground 85 86 Ground Odd External Ref 87 88
J10 - Pods 1(Odd) and 2 (Even) Signal name/Logical Signal Name SDA SB_L7_B3_9 SB_L8_B3_9 SB_L7_B4_10 SB_L8_B2_8 SB_L8_B4_10 SB_L9_B3_9 SB_L7_B2_8 SB_L9_B1_7 SB_L5_B4_10 SB_L7_B1_7 SB_L5_B2_8 SB_L2_B0_6 SB_L0_B0_6 SB_L1_B1_7 Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Ground 1 2 Ground SM 3 4 SM Ground 5 6 Ground Odd D0 7 8 Even D0 Ground 9 10 Ground Odd D1 11 12 Even D1 Ground 13 14 Ground Odd D2 15 16 Even D2 Ground 17 18 Ground
Signal name/Logical Signal Name SB_L6_B2_8 SB_L6_B4_10 Anly_clk1p Anly_clk1n Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Ground 61 62 Ground Odd D14 63 64 Even D14 Ground 65 66 Ground Odd D15 67 68 Even D15 Ground 69 70 Ground NC 71 72 NC Ground 73 74 Ground NC 75 76 NC Ground 77 78 Ground Odd D16P/Odd CLK 79 80 Even DP16P/Even CLK Ground 81 82 Ground Odd DP16N/Odd CLKN 83 84 Even DP16N/Even CLKN Ground 85 86 Ground Odd Extern
J13 Pods 1(Odd) and 2 (Even) Signal name/Logical Signal Name NB_L12_B1_7 NB_L12_B2_8 NB_L12_B3_9 NB_L12_B5_11 NB_L12_B4_10 NB_L12_B0_6 SB_L5_B3_9 SB_L1_B3_9 SB_L1_B5_11 SB_L4_B1_7 SB_L3_B5_11 SB_L3_B2_8 SB_L0_B5_11 Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Ground 1 2 Ground NC 3 4 NC Ground 5 6 Ground Odd D0 7 8 Even D0 Ground 9 10 Ground Odd D1 11 12 Even D1 Ground 13 14 Ground Odd D2 15 16 Even D2 Ground 17 18 Ground Odd D3 19
Signal name/Logical Signal Name SB_L4_B0_6 SB_L3_B0_6 SB_L3_B1_7 TRIGGER3 GND Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Odd D13 59 60 Even D13 Ground 61 62 Ground Odd D14 63 64 Even D14 Ground 65 66 Ground Odd D15 67 68 Even D15 Ground 69 70 Ground NC 71 72 NC Ground 73 74 Ground NC 75 76 NC Ground 77 78 Ground Odd D16P/Odd CLK 79 80 Even DP16P/Even CLK Ground 81 82 Ground Odd DP16N/Odd CLKN 83 84 Even DP16N/Even CLKN Ground
General Information This chapter provides additional reference information including the characteristics and signal connections for the FS2343 FBDIMM Interposer Probe. The following operating characteristics are not specifications, but are typical operating characteristics. Probe Connection 240 pin gold finger card edge connection at target (bottom) end of probe and card edge socket at the top edge of the probe both conforming to JEDEC spec MO-224.
