User manual

lpErrorDoc.txt
Digital module: {name}. Report this error to Agilent Technologies.
This error is reported when the FPGAs on the digital module FPGAs
failed to be configured. The digital module will not work properly
in this state.
801 Digital module VCO unlock error; The VCO on the digital module is
unlocked. Check to make sure the clock settings are correct and the
correct clock reference is connected.
The VCO on the digital module is unlocked. Check to make sure the
clock settings are correct and the correct clock reference is
connected.
802 Digital module overrange error; The output data is being clipped by the
resampler. Reduce the scaling under the data menu to correct this
problem.
This error is reported when the output of the resampler is being
clipped.
803 Digital module input FIFO overflow error; There are more samples being
produced than can be consumed at the current clock rate. Verify that
the digital module clock is set up properly.
This error is reported when the digital module clock setup is not
synchronized with the rate the samples are entering the digital
module. Verify that the input clock rate matches the specified
clock rate under the clock setup menu.
804 Digital module input FIFO underflow error; There are not enough samples
being produced for the current clock rate. Verify that the digital
module clock is set up properly.
This error is reported when the digital module clock setup is not
synchronized with the rate the samples are entering the digital
module. Verify that the input clock rate matches the specified
clock rate under the clock setup menu.
805 Digital module output FIFO overflow error; There are more samples being
produced than can be consumed at the current clock rate. Verify that
the digital module clock is set up properly.
This error is reported when the output FIFO is overflowing in the
digital module. This error can be generated if and external clock
or its reference is not set up properly, or if the internal VCO is
unlocked.
806 Digital module output FIFO underflow error; There are not enough
samples being produced for the current clock rate. Verify that the
digital module clock is set up properly.
This error is reported when the output FIFO is underflowing in the
digital module. This error can be generated if and external clock
or its reference is not set up properly, or if the internal VCO is
unlocked.
807 Unexpected digital module interface FPGA; The interface FPGA on the
digital module is not up to date and needs to be updated to insure
proper operation. Please refer to the manual for details on updating
the module's interface FPGA.
This error is reported when and ssio interface FPGA is found with a
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