Specifications

5
16850 Series Logic Analyzer Specifications and Characteristics
16851A 16852A 16853A 16854A
Number of channels 34 (1 clock +
1 clock qualifier)
68 ( 1 clock +
3 clock qualifiers)
102 (1 clock +
3 clock qualifiers)
136 (1 clock +
3 clock qualifiers)
Deep timing (asynchronous) sampling mode Conventional and transitional timing
(up to 128 M depth)
Maximum sample rate in full channel mode (nom) 2.5 GHz
Maximum sample rate in half channel mode (nom) 5 GHz
Sample period on all channels (nom) 400 ps to 10 ns
Sample period in half channel mode (nom) 200 ps
Minimum data pulse width (nom) 1 sample period + 200 ps
Maximum time between transitions (nom) 66 days
Time interval accuracy within a 16 channel pod (typ)
1
± (1 sample period + 130 ps + 0.01% of time interval reading)
Time interval accuracy across 16 channel pods (typ)
1
± (1 sample period + 400 ps + 0.01% of time interval reading)
1. With single-ended flying lead and Soft Touch Pro probes.
Timing zoom (captured simultaneously with timing or state sampling mode capture)
Timing analysis sample rate (nom) 12.5 GHz (80 ps sample resolution)
Time interval accuracy (nom)
Within a 16 channel block
Between 16 channel blocks
± (80 ps + 130 ps + 0.01% of time interval reading)
± (80 ps + 400 ps + 0.01% of time interval reading)
Memory depth (nom) 256 K samples
Trigger position (nom) Start, center, end, or user-defined
Minimum data pulse width (nom) 1 sample period + 200 ps
State (synchronous) sampling mode
Maximum state data rate ― base (spec) 700 Mb/s using both edges of clock (spec)
Maximum state data rate ― Option 700 (spec) 1.4 Gb/s using both edges of clock (spec)
Maximum state clock frequency ― single edge clocking ― base (typ) 350 MHz
Maximum state clock frequency ― single edge clocking ― Option 700 (typ) 700 MHz
Minimum state clock frequency (typ)
1
12.5 MHz (single edge)
6.25 MHz (both edges)
Minimum data valid window (typ)
2
160 ps
Sample position adjustment resolution (typ) 20 ps
Sample position adjustment accuracy (typ) ± 150 ps
Minimum data valid window (typ)
1
160 ps
Minimum setup time (typ) 80 ps
Minimum hold time (typ) 80 ps
Minimum eye height (typ) 160 mV
Sample position adjustment range (typ) 7 ns
Minimum state clock pulse width single edge (typ) 200 ps
Minimum time between active clock edges ― standard (typ) 1429 ps
Minimum time between active clock edges ― Option 700 (typ) 714 ps
Maximum time between active clock edges (typ)
1
80 ns (single edge)
Clock qualifier setup time (typ) 200 ps
Clock qualifier hold time (typ) 200 ps
Time tag resolution (typ) 80 ps
Maximum time count between stored states (nom) 66 days
1. Clock can pause for up to 66 days once every 8 or more edges.
2. Dependent on probing system.