User`s guide

516 Appendix B
Status Reporting System
Status Register Structure
Issuing the *CLS command will clear all bits from the status byte register.
Table B-1 Status Bit Definitions of Status Byte Register
Bit
Position
Name Description
0, 1 Not used Always 0
2
Error/Event Queue
Set to “1” if the error/event queue contains data; reset to
“0” when all the data has been retrieved.
3 Questionable Status Register
Summary
Set to “1” when one of the enabled bits in the status event
status register is set to “1.”
4 MAV (Message Available) Set to “1” when the output queue contains data; reset to
“0” when all the data has been retrieved.
5 Standard Event Status Register
Summary
Set to “1” when one of the enabled bits in the status event
status register is set to “1.”
6 RQS Set to “1” when any of the status byte register bits enabled
by the service request enable register is set to “1”; reset to
“0” when all the data has been retrieved through serial
polling.
7 Operation Status Register
Summary
Set to “1” when one of the enabled bits in the operational
status register is set to “1.”