Programming instructions

Programming the Status Register System
Status Groups
Chapter 3142
Data Questionable BERT Condition Register
The Data Questionable BERT Condition Register continuously monitors the hardware and
firmware status of the signal generator. Condition registers are read only.
Data Questionable BERT Transition Filters (negative and positive)
The Data Questionable BERT Transition Filters specify which type of bit state changes in the
condition register set corresponding bits in the event register. Changes can be positive (0 to 1)
Table 3-12 Data Questionable BERT Condition Register Bits
Bit Description
0 No Clock. A 1 in this bit indicates no clock input for more than 3 seconds.
1 No Data Change. A 1 in this bit indicates no data change occurred during the last 200 clock
signals.
2 PRBS Sync Loss. A 1 is set while PRBS synchronization is not established. *RST sets the bit
to zero.
3−10 Unused. These bits are always set to 0.
11 Down conv. / Demod Unlocked. A 1 in this bit indicates that either the demodulator or the
down converter is out of lock.
12 Demod DSP Ampl out of range. A 1 in this bit indicates the demodulator amplitude is out
of range. The *RST command will set this bit to zero (0).
13 Sync. to BCH/TCH/PDCH. If the synchronization source is BCH, a 1 in this bit indicates
BCH synchronization is not established it does not indicate the TCH/PDCH synchronization
status. If the sync source is TCH or PDCH, a 1 in this bit indicates that TCH or PDCH
synchronization is not established. *RST sets the bit to zero.
14 Waiting for TCH/PDCH. A 1 in this bit indicates that a TCH or PDCH midamble has not
been received. This bit is set when bit 13 is set. The bit is also set when the TCH or PDCH
synchronization was once locked and then lost (in this case the front panel displays
“WAITING FOR TCH (or PDCH)”. *RST set the bit to zero.
15 Always 0.
Query: STATus:QUEStionable:BERT:CONDition?
Response: The decimal sum of the bits set to 1