Specifications

566 Appendix B
GPIB Status Report System
Status Register Structure
When the *CLS command is executed, each bit in the Questionable Status Hardware Event
Register is cleared.
When the *CLS command is executed, each bit in the Questionable Status Limit Event
Register is cleared.
Table B-5 Status Bit Definition of Questionable Status Hardware Event Register
Bit
position
Name Description
0 Not used Always 0.
1 PLL Unlocked Set to 1 when an unlocked phase lock loop has been
detected in the E4991A.
2 DC Bias Overload Set to 1 when dc bias current exceeding the maximum
current limit is supplied or dc bias voltage exceeding
the maximum voltage limit is detected.
3 RF Overload Set to 1 when overload has been detected in the
E4991A internal circuit.
4-15 Not used Always 0.
Table B-6 Status Bit Definition of Questionable Status Limit Event Register
Bit
position
Name Description
0 Not used Always 0.
1 Trace 1: Marker Limit Test Fail Set to 1 when the marker limit test has failed in trace 1.
2 Trace 2: Marker Limit Test Fail Set to 1 when the marker limit test has failed in trace 2.
3 Trace 3: Marker Limit Test Fail Set to 1 when the marker limit test has failed in trace 3.
4 Trace 4: Marker Limit Test Fail Set to 1 when the marker limit test has failed in trace 4.
5 Trace 5: Marker Limit Test Fail Set to 1 when the marker limit test has failed in trace 5.
6-15 Not used Always 0