Specifications

Appendix B 563
GPIB Status Report System
Status Register Structure
B. GPIB Status Report System
When the *CLS command is executed, each bit in the Status Byte Register is cleared.
Table B-1 Status Bit Definition of Status Byte Register
Bit
position
Name Description
0-1 Not used Always 0.
2 Error/Event Queue Set to 1 when the error/event queue contains data; reset to
0 when all of the data has been retrieved.
3 Questionable Status Register
Summary Bit
Set to 1 when one of the enabled bits in the Questionable
Status Register is set to 1.
4 MAV (Message Available) Set to 1 when there is information waiting to be output
and still not read. When the information is read, this bit is
set to 0.
5 Standard Event Status Register
Summary Bit
Set to 1 when one of the enabled bits in the Standard
Event Status Register is set to 1.
6 RQS (Serial poll is used to read
the Status Byte Register)
Set to 1 when E4991A generates SRQ. When the Status
Byte Register is read by serial poll, this bit is set to 0.
MSS (*STB? is used to read the
Status Byte Register)
Set to 1 when one of the bits in the Status Byte Register
enabled by the Service Request Enable Register is set to 1.
7 Operation Status Register
Summary Bit
Set to 1 when one of the enabled bits in the Operation
Status Register is set to 1.