Specifications

558 Appendix B
GPIB Status Report System
General Model of Status Registers
Status Byte Register
When an event register bit enabled by the corresponding enable register bit is set to 1, the
corresponding summary bit in the Status Byte Register is also set to 1. In addition to the
summary bit for the event register, the Status Event Register has a bit indicating the status
of the output queue and a bit indicating SRQ status.
The Status Byte Register value can be read with the *STB? command or serial poll
(SPOLL statement in HTBasic) from the controller.
When the *STB? command is used to read the Status Byte Register, the content of the
register is not changed. On the other hand, when the SPOLL statement in HTBasic is used
to read a Status Byte Register, the RQS bit in the Status Byte Register is cleared.
Table B-1 shows the content of the Status Byte Register in the E4991A. The serial poll
reads bit 6 of the Status Byte Register as an RQS bit. On the other hand, the *STB?
command reads bit 6 as an MSS bit. For details on RQS and MSS bits, refer to Table B-1.
In addition, by setting the bit(s) in the Service Request Enable Register, service requests
can be generated in conjunction with the Status Byte Register.