User`s manual

Changing the Output Frequency
This section explains how the frequency of the output signal is changed
instantaneously by writing frequency codes to the appropriate registers.
The section shows how to change the frequency when either the
direct-digital-synthesis (
[SOURce:]FREQuency[1]) or divide-by-n
(
[SOURce:]FREQuency2) frequency synthesis method is used.
The Frequency
Control Registers
The following Frequency Control Registers are used to change the output
frequency generated with the direct-digital-synthesis (DDS) and divide-by-n
methods:
• Phase Increment Registers (DDS):
base_addr + A7
16
through base_addr + A1
16
• Frequency Load Strobe Register (DDS):
base_addr + 8D
16
• Sample/Hold and ROSC/N Control Register (DIV N):
base_addr + 63
16
• ROSC/N Divider Registers (DIV N):
base_addr + 7D
16
through base_addr + 7F
16
The Phase Increment
Registers
Phase Increment Registers A7, A5, A3, and A1 contain the 32-bit phase
increment data that is written to the DDS micro-chip. The phase increment
value determines the output frequency.
Address 15–8 76543210
base + A7
16
through
base + A1
16
unused frequency value
Register A7: Bits 31–24 of the phase increment value. These are the most
significant bits (MSBs).
Register A5: Bits 23–16 of the phase increment value.
Register A3: Bits 15–8 of the phase increment value.
Register A1: Bits 7–0 of the phase increment value. These are the least
significant bits (LSBs).
Appendix C Register-Based Programming 487