User`s manual

<unmask> is the decimal, hexadecimal (#H), octal (#Q), or binary (#B)
value of the Condition Register bit to be unmasked. (The decimal values of
bits 5 and 8 are 32 and 256.)
The Event Register The Event Register latches transition events from the Condition Register as
specified by the Transition Filter. Bits in the Event Register are latched and
remain set until the register is cleared by one of the following commands:
STATus:QUEStionable[:EVENt]?
*CLS
The Enable Register The Enable Register specifies which bits in the Event Register can generate
a summary bit which is subsequently used to generate a service request.
The AFG logically ANDs the bits in the Event Register with bits in the
Enable Register, and ORs the results to obtain a summary bit.
The bits in the Enable Register that are to be ANDed with bits in the Event
Register are specified (unmasked) with the command:
STATus:QUEStionable:ENABle <unmask>
<
unmask> is the decimal, hexadecimal (#H), octal (#Q), or binary (#B)
value of the Enable Register bit to be unmasked. (The decimal values of
bits 5 and 8 are 32 and 256.)
The Enable Register is cleared at power-on, or by specifying an
<unmask>
value of 0.
Program Example The QSSG_RQS program sets up the Questionable Signal Status Group
Registers to monitor the output frequency generated by the
[SOURce:]FREQuency2 subsystem. If the programmed frequency differs
from the actual output frequency by greater than 1%, a service request
interrupt is sent to the computer which responds with a message indicating
the condition.
The steps of the program are:
1. Set the bit transition which will latch the event (frequency error) in
the Event Register.
STATus:QUEStionable:NTRansition <unmask>
or
STATus:QUEStionable:PTRansition <unmask>
432 AFG Status Chapter 9