User manual

Register-Based Programming 101Appendix B
A16 Address Space
Inside the Command
Module or Mainframe
When the A16 address space is inside the E1406A Command Module (see
Figure B-2), the multiplexer’s base address is computed as:
1FC000
16
+ (LADDR * 64)
16
or 2,080,768 + (LADDR * 64)
10
where 1FC000
16
(2,080,768) is the starting location of the VXI A16
addresses, LADDR is the multiplexer’s logical address, and 64 is the
number of address bytes per register-based device. The multiplexer’s
factory set logical address is 112. If this address is not changed, the
multiplexer will have a base address of:
1FC000
16
+ (112 * 64)
16
= 1FC000
16
+ 1C00
16
= 1FDC00
16
or 
2,080,768 + (112 * 64) = 2,080,768 + 1536 = 2,087,936
Register Offset The register offset is the register’s location in the block of 64 address bytes.
For example, the multiplexer’s Status/Control Register has an offset of 04
16
.
When you write a command to this register, the offset is added to the base
address to form the register address:
DC00
16
+ 04
16
= DC04
16
1FDC00
16
+ 04
16
= 1FDC04
16
or
56,320 + 4 = 56,324
2,087,936 + 4 = 2,087,940
Figure B-2. Registers Within E1406 A16 Address Space
+ (Logical Address 64)
2,080,768 + (Logical Address 64)
Register Address = Base address + Register Offset
200000
IF0000
000000
Base Address = IFC000
IFOOOO
16
ADDRESS
SPACE
E1406A
ADDRESS MAP
FFFFFF
EOOOOO
16
16
A24
16
A16
ADDRESS
SPACE
IFCOOO
16
200000
*
A16 REGISTER MAP
E1460A
Status/Control Register
Device Type Register
(2,080,768)
IFCOOO
or
*
O4
O2
OO
10
16
16
16
16
ID Register
SPACE
ADDRESS
REGISTER
200000
16
OFFSET
REGISTER
20
22
24
26
3E
3C
16
16
16
16
16
16
16-BIT WORDS
16
16
16
16
16
*
*
Bank 9 Control Register
16
28
16
2A
16
2C
16
2E
16
30
Bank 7 Control Register
Bank 6 Control Register
Bank 5 Control Register
Bank 4 Control Register
Bank 3 Control Register
Bank 2 Control Register
Bank 1 Control Register
Bank 0 Control Register