Specifications

The WRITE
Registers
The following WRITE registers are located on the FET strain gage
multiplexer.
• Control Register (base + 04
16
)
• Scan Control Register (base + 06
16
)
• Scan Channel Delay Register (base + 08
16
)
• Scan Channel Configuration Register (base + 0A
16
)
• Direct Channel Configuration Register (base + 0C
16
)
• Direct Control Register (base + 0E
16
)
Control Register The Control Register is used to reset the multiplexer, enable interrupts,
choose direct or scan list control of the channels, and to internally trigger
channel closing.
base + 04
16
1514131211109876543210
Write Undefined X X X TRG
INT
DIR IRQ
EN
X CRD
RST
CRD RST Card Reset. Writing a one (1) to bit 0 resets the multiplexer. Writing a
zero turns the reset function off. You must write a zero after a reset or the
multiplexer will not operate. The Reset conditions are: all enables are set
false (0), clear scan list, scan mode enabled (direct bit set 0), delay is
1 µsec and all channels opened.
IRQ EN Interrupt Request Enable (Write). A one (1) enables the card to generate
interrupts, a zero (0) disables it.
DIR Direct. Selects between direct control and scan list control. A zero (0)
indicates scan list control and a one (1) indicates direct control. For scan
list control, the Direct Registers (base + 0C, base + 0E) are invalidated. For
direct control, the Scan Channel Configuration Register is invalidated. The
scan list, however, is not affected.
TRG INT Trigger Internal. A one (1) immediately advances a channel on the scan
list, a zero (0) is the idle state. Bit is automatically set back to zero (0) upon
channel advance.
Appendix D Strain Gage Register-Based Programming 129
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