User`s manual

Index 151
P (continued)
Ports (continued)
peripheral interrupt request (PIR) line
, 43
reset (RES) line, 43
specifying, 14
specifying multiple
, 15, 37, 53
status (STS) line
, 43
transfer control register, 113
transfer mode
, 116
type combinations allowed, 55
writing data to, 83–84
Primary Address, 31
Program Examples
combine all 4 ports, 37
input data bits and bytes
, 35
output data bits and bytes, 36
reading
an 8-bit byte, 128–129
registers, 123–124
register access, 121
resetting the module
, 122
set the handshake mode, 34
system configuration, 121
trace memory, 38–39
using
non-data I/O lines, 136
PIR interrupt lines
, 132
verify initial operation, 16
writing
a 16-bit word, 127
an 8-bit byte, 125–126
Programming
debugging register-based
, 130
the Digital I/O module, 13–15
using SCPI, 13–15
Pull-up
calculating resistor value, 28
discrete resistive, 29
enable jumpers
, 19
external, 28–29
internal, 19, 29
resistor, 19, 28
PULSe Handshake Mode, 34, 44, 47, 78, 80–81,
87–89, 117
Q
Query
data
bits
, 77
blocks available, 90
lines polarity
, 82
error register
, 97
external memory state, 71
flag line
polarity
, 86
status, 67
handshake
delay time, 79, 88
mode, 81, 89
I/O
control line, 89
memory block size, 92
module description, 96
monitor mode state, 63
operation
event status register, 94
status condition register
, 94
questionable status
condition register, 95
event register, 95
register, 95
SCPI version, 97
VME memory
address
, 69
size, 70
Questionable Status
condition register, 95
enable register, 94
event register
, 95
register, 93
query mask set, 95
R
Range Multipliers, 117
*RCL, 98
Reading
a 16-bit word, 130
an 8-bit byte, 128–129
data from memory block
, 91
operation
event status register, 94
status condition register, 94
questionable status
condition register, 95
event register
, 95
registers, 123–124