Agilent 75000 Series B Agilent E1330B Quad 8-Bit Digital I/O Module User’s Manual and SCPI Programming Guide Where to Find it - Online and Printed Information: System installation (hardware/software) ............VXIbus Configuration Guide* Agilent VIC (VXI installation software)* Module configuration and wiring .......................This Manual SCPI programming ............................................. This Manual SCPI example programs .....................................
Contents Agilent E1330B User’s Manual Warranty ....................................................................................................................... 5 Safety Symbols ............................................................................................................. 6 WARNINGS ................................................................................................................. 6 Declaration of Conformity .................................................................
Chapter 4 Understanding the Agilent E1330B Digital I/O Module .......................................... 41 Using This Chapter ..................................................................................................... 41 Port Description .......................................................................................................... 41 Data Lines ........................................................................................................... 41 The FLG Line (Input) ..........
Chapter 5 Agilent E1330B Digital I/O Module Command Reference (continued) MEMory Subsystem (continued) :VME:SIZE? ........................................................................................................ 70 :VME:STATe ...................................................................................................... 71 :VME:STATe? .................................................................................................... 71 [SOURce:] Subsystem .....................................
Chapter 5 (continued) SYSTem Subsystem ................................................................................................... 96 :CDEScription? ................................................................................................... 96 :CTYPe? .............................................................................................................. 96 :ERRor? ...............................................................................................................
Certification Agilent Technologies, Inc. certifies that this product met its published specifications at the time of shipment from the factory. Agilent Technologies further certifies that its calibration measurements are traceable to the United States National Institute of Standards and Technology (formerly National Bureau of Standards), to the extent allowed by that organization's calibration facility, and to the calibration facilities of other International Standards Organization members.
Documentation History All Editions and Updates of this manual and their creation date are listed below. The first Edition of the manual is Edition 1. The Edition number increments by 1 whenever the manual is revised. Updates, which are issued between Editions, contain replacement pages to correct or add additional information to the current Edition of the manual. Whenever a new Edition is created, it will contain all of the Update information for the previous Edition.
DECLARATION OF CONFORMITY According to ISO/IEC Guide 22 and CEN/CENELEC EN 45014 Manufacturer’s Name: Manufacturer’s Address: Agilent Technologies, Incorporated th 815 – 14 St. SW Loveland, Colorado 80537 USA Declares, that the product Product Name: Model Number: Product Options: Quad 8 Bit Digital I/O E1330B This declaration covers all options of the above product(s).
Notes: 8
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Chapter 1 Getting Started Using This Chapter This chapter describes the Quad 8-bit Digital I/O Module and how to program the Module using SCPI (Standard Commands for Programmable Instruments) commands. This chapter contains the following sections: • Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • Instrument Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • Downloading SCPI Drivers . . . . . . . . . . . . . . . . . . . . . . . . .
Each port is identical and consists of 6 control lines and 8 data lines. There are 7 registers for control and status on each port. In addition, the module also has Manufacturer ID, Device Type, and Module Status/Control Registers. Figure 1-1 shows the locations of the ports and a simplified diagram of a single port. Of the seven control lines, three (I/O, CTL, and FLG) are used with SCPI commands and three (RES, STS, and PIR) are controlled through register access.
Instrument Definition Each Digital I/O module installed in an Agilent mainframe is treated as an independent instrument; having a unique secondary GPIB address. Each instrument is also assigned a dedicated error queue, input and output buffers, status registers and, if applicable, dedicated mainframe memory space for readings or data. Multiple Digital I/O modules cannot be combined into a single instrument.
SCPI Command Format Used in This Manual SCPI commands can be used in either long or short form. A long form example is: DISPlay:MONitor ON The same command, without the lower case letters, is the short form. For example: DISP:MON ON Either the long form or the short form commands can be used to perform the same result. The long and short forms can also be mixed within the same program code. The commands are case insensitive, either upper or lower case letters are accepted.
Specifying a Bit Each of the four ports on the module has eight bi-directional data lines, corresponding to eight programmable data bits. Some SCPI commands allow you manipulate or read these bits individually. For example: MEASure:DIGital:DATAn:BITm? This command reads the state of a bit, specified by m, on port n. The result will be either 0 or 1, indicating the current logical state of the bit.
Initial Operation Use the following example to verify initial operation. The example first sets and then queries the polarity of a logical true condition on the port 0 FLG line. The example uses an HP Series 200/300 Computer with BASIC as the programming language. The computer is connected to an Agilent E1301 Mainframe using the General Purpose Interface Bus (GPIB)*.
Chapter 2 Configuring the Agilent E1330B Digital I/O Module Using This Chapter This chapter shows how to configure the Digital I/O module for use in a VXIbus mainframe, connect peripheral devices, and configure the module for operation. Refer to Figure 2-1 for locations of jumpers and switches. This chapter contains the following sections: • Setting the Address Switch . . . . . . . . . . . . . . . . . . . . . . . . . . • Enabling Pull-ups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting the Address Switch Refer to Figure 2-1. In the center rear of the module, next to the P1 connector, you will find the logical address switch. Its factory setting is 144; rockers 4 and 7 are closed, all others are open. You can select the address of the Digital I/O module to any number 0–255 (decimal). The default setting of the address switch is shown in Figure 2-2.
Enabling Pull-ups Referring to Figure 2-1, note the pull-up enable jumpers near the middle of each of the large ICs. The data lines of each port can be independently configured for either passive or active pull-up to TTL high levels. The factory-shipped condition is pull-up disabled for all ports. The data lines may be either inputs or outputs. When the data lines are outputs, and the jumper is in the enabled position, the outputs are actively forced high.
Selecting the Interrupt Line The VXI peripheral interrupt bus consists of seven lines which can carry the interrupt signal to the commander. The most common line to be used is line one, as this is the usual default interrupt line. Many VXIbus commanders have a way to change the interrupt line they manage (for example, the E1405/06 has an interrupt line allocation table).
Combining the Flag Lines Each port contains a Flag Line, labeled FLG, that can be used to implement a handshake scheme with a peripheral. For single port operations, the FLG lines can be used in the factory default setting (no flag lines combined) to handshake with a peripheral. For multi-port operations with a single handshake line, you can combine the flag line from multiple ports. The combined flag lines are physically tied together.
Digital I/O Module Peripheral Pinout Figure 2-6 shows pinouts for the Digital I/O module connectors. Each is compatible with easy crimp connections to ribbon cables for standard digital I/O interfacing. Figure 2-7 shows the data line location on the supplied ribbon cables. Figure 2-8 shows how to connect the cables.
Figure 2-6.
Figure 2-7. Data Line Location on Ribbon Cables Figure 2-8.
Configuring for Isolated Digital I/O The two Digital I/O module peripheral connectors, J1 and J2, each have 60 pins. An industry standard isolated digital I/O peripheral, like the Opto 22 16 Position Single Channel Mounting Rack, is a 50-pin connection. The connector is either a card edge or a header connector (similar to J1 on the Digital I/O module). For example, the Opto 22 rack, PB16C, uses a card edge connector; PB16H uses a header connector. They both have the same pin-out for the ribbon cable.
Connecting to a GPIO Peripheral The GPIO interface is a widely used standard parallel interface for connecting computers to peripherals. The GPIO interface may employ up to 32-bits of bi-directional data transfer. The Digital I/O module and the GPIO interface have identical line definitions but different pin assignments. Ports A-D on the GPIO are defined as ports 0-3 on the Digital I/O module. Procedure 1. Connect the ribbon cable to connector J1 and/or J2 on the Digital I/O module. 2.
Table 2-1.
Using with External Pull-ups The Digital I/O module data lines can be used in an open collector configuration. Connections for open collector require the use of external power supplies and pull-up resistors. The internal pull-up mode of the Digital I/O module should be disabled for open collector output. Figure 2-10 shows a single data line connection. The value of the pull-up resistor is calculated as follows: Vcc = 5.0 Vdc Imax = Iout Low × safety_factor = 48mA × 0.
Typical Connection Figure 2-11 shows a typical driver/receiver connection for data transfer. The FLG, PIR, and STS lines have a discrete resistive pull-up network. The data lines do not have a discrete resistive pull-up, but can use an internal pull-up in the 75ALS160. The internal pull-up requires that the data lines sink 3.2 mA to pull the line to less than 0.4 V. The I/O, CTL, and RES lines are open collector, and require external pull-up to logic high. Figure 2-11.
Notes: 30 Configuring the Agilent E1330B Digital I/O Chapter 2
Chapter 3 Using the Agilent E1330B Digital I/O Module Using This Chapter This chapter is divided into eight sections about transferring data to and from the Digital I/O Module and a peripheral: • Addressing the Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • Operation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • Default and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . • Setting the Polarity . . . . . . . . . . . . . . . . . . . . . . .
Operation Overview The following steps illustrate general operation of the Digital I/O module. Figure 3-1.
Default and Reset States At initial power-on and following the *RST command, the Digital I/O module is set to the following states: CTL line: 0 = TTL Low I/O line: TRUE = input = TTL High Data, FLG, and CTL line Polarity: POSitive Handshake mode: NONE Setting the Polarity The logical true level of the control (CTL) line, the flag (FLG) line, and the data lines of each port can be set to either TTL high (> 2.5V) or TTL Low (< 1.4V) levels.
Setting the Handshake Mode Handshaking ensures correct transfer of data between devices. You must set both the mode and the timing to establish correct handshaking. Most handshake modes use the FLG and CTL lines to control the data transfer.
Inputting Data Bytes and Bits Data input is performed using commands in the SCPI MEASure:DIGital:DATA n subsystem. The returned value of an input will depend upon the POLarity programmed for the port. Both Input and Output operations will attempt to complete the handshake mode set for the port and may "hang" if required handshake operations are not completed. To unhang a hung transfer, issue a IEEE 488 selected device clear. In BASIC this is CLEAR 70918.
Outputting Data Bytes and Bits Data output is performed using the commands in SCPI [SOURce:]DIGital:DATAn subsystem. The TTL levels of an output will depend upon the POLarity programmed for the port. Both Input and Output operations will attempt to complete the handshake mode set for the port and may "hang" if required handshake operations are not completed. To unhang a hung transfer, issue a IEEE 488selected device clear. In BASIC this is CLEAR 70918.
Multiple Port Operations The Digital I/O module supports multiple port operations using a single SCPI command. Multiple port operations are shown in the SCPI command syntax as the optional keyword [:type]. For example, this SCPI command syntax initiates a handshake and returns a value: MEAS:DIG:DATAn[:type]? The optional keyword [:type] is replaced by one of the following keywords: Example :BYTE This keyword, or no keyword (default), is used for 8-bit port operations.
Using Trace Memory Trace memory can speed input and output operations and free your system controller during multiple byte input or output operations. A portion of system memory is set aside and data is read or written as blocks. Trace memory allows the fastest operation of the Digital I/O module. The rate of transfer of each block of data is determined by the handshake speed of the Digital I/O module and the peripheral. Note Trace Memory Example 1 Byte swapping may occur when using the :TRACe commands.
Trace Memory Example 2 This example writes 20 bytes as 10 WORDS at ports 0 and 1 as in the first example, it uses an external VME memory board. 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 Trace Memory Example 3 This example reads 40 WORDS from ports 0 and 1. 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Chapter 3 RE-SAVE "Trace_2" ASSIGN @ Dio TO 70918 INTEGER A(1:10) ,Ready DATA 65,66,67,68,69,70,71,72,73,74 !A, B, C, D, E, F, G, H, I, J.
Notes: 40 Using the Agilent E1330B Digital I/O Module Chapter 3
Chapter 4 Understanding the Agilent E1330B Digital I/O Module Using This Chapter This chapter provides explanations of the signal lines, handshake modes, and port combining for the Digital I/O Module. This chapter has the following topics. • Port Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • Default and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . • Setting the Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The FLG Line (Input) The CTL Line (Output) The I/O Line (Output) Each port has a flag (FLG) line. A flag line is an input line from a peripheral and has two states: READY and BUSY. A flag line is normally used in conjunction with the corresponding control line (CTL) to establish a handshake between a peripheral and the Digital I/O Module. SCPI commands that define handshake modes typically use the FLG and CTL lines.
The STS Line Each port has a status line labeled STS. The STS line is an input line to the Digital I/O module. The use of the STS line is only at the register level, and is not supported by SCPI commands. Refer to Appendix B for more information about this line. The PIR Line Each port has a peripheral interrupt request line labeled PIR. The PIR line is an input line to the Digital I/O module. The use of the PIR line is only at the register level, and is not supported by SCPI commands.
Using the Handshake Modes Handshaking ensures correct transfer of data between devices. You must set both the mode and the timing to establish correct handshaking.
Handshake Modes The operation of each handshake mode for input or output operations is described in the following subsections. In these discussions, only the FLG, CTL, and DATA lines are included. Other port control lines, controlled only through register access, are described in Appendix B of this manual. LEADing Edge The LEADing Edge handshake makes use of both the CTL and FLG lines. The input and output operations are described below.
TRAiling Edge The TRAiling Edge handshake makes use of both the CTL and FLG lines. The input and output operations are described below. INPUT 46 OUTPUT 1 The Digital I/O module senses the FLG line and waits for READY. 1 The Digital I/O module checks the state of the FLG line (must be READY). 2 The Digital I/O module sets the I/O line HIGH. 2 The Digital I/O module sets the I/O line LOW. 3 The Digital I/O module sets CTL TRUE. 3 The Digital I/O module places the data on the data lines.
PULSe The PULSe handshake makes use of both the CTL and FLG lines. The input and output operations are described below. INPUT Chapter 4 OUTPUT 1 The Digital I/O module senses the FLG line and waits for READY. 1 The Digital I/O module checks the state of the FLG line (must be READY). 2 The Digital I/O module sets the I/O line HIGH. 2 The Digital I/O module sets the I/O line LOW. 3 The Digital I/O module sets CTL TRUE. 3 The Digital I/O module places the data on the data lines.
PARTial The PARTial handshake makes use of both the CTL and FLG lines. The input and output operations are described below. INPUT 1 The Digital I/O module sets the I/O line HIGH. 1 The Digital I/O module sets the I/O line LOW. 2 The Digital I/O module sets CTL TRUE. 2 The Digital I/O module places the data on the data lines. 3 The peripheral senses the CTL line and sets the data lines. 3 After waiting the programmed delay time, Td, the Digital I/O module sets CTL to TRUE.
STRobe The STRobe handshake makes use the CTL line, but not the FLG line. The input and output operations are described below. INPUT NONE OUTPUT 1 The Digital I/O module sets the I/O line HIGH. 1 The Digital I/O module sets the I/O line LOW. 2 The Digital I/O module sets CTL TRUE. 2 The Digital I/O module places the data on the data lines. 3 The peripheral senses the CTL line and sets the data lines. 3 After waiting the programmed delay time, Td, the Digital I/O module sets CTL to TRUE.
Inputting Data Bytes and Bits Data input is performed using commands in the SCPI MEASure:DIGital:DATA n subsystem. The returned value of an input will depend upon the POLarity programmed for the port. Input operations can involve single bits, 8-bit bytes, or multiple bytes. Single bit input operations always return a decimal value of 0 or 1. Byte or multiple byte input operations always return numbers in decimal format.
(POSitive polarity) if all data lines are at a TTL low level, the returned value will be 0; if all lines are at a TTL high level, the returned value will be 255. For example, the following BASIC program code will request and display the decimal value of the data lines on port 2. 120 130 140 OUTPUT @Dio;"MEAS:DIG:DATA2?" ENTER @Dio;Result DISP "Decimal value of port 2 data lines ";Result Port numbers range from 0 to 3 for single port operations.
operations. For a single port, the data lines number and bit numbers are: Dn-7 Dn-6 Dn-5 Dn-4 Dn-3 Dn-2 Dn-1 Dn-0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 In this manual the physical data lines are indicated as Dn-1. The n should be replaced with the port number for the input operation. For example, bit 3 of port 2 affects the state of data line D2-3.
Multiple Port Operations The Digital I/O module supports multiple port operations. You can combine operations using 2 or 4 ports with a single SCPI command. Multiple port operations are shown in the SCPI command syntax as the optional keyword [:type] .
Multiple port handshaking has the following two abnormalities regarding the CTL and FLG control lines: • Input or Output handshaking using the CTL line. The CTL line is set TRUE or FALSE sequentially on all ports involved in the operation, from the lowest numbered port to the highest numbered port. A slight time delay exists between each port setting the CTL line TRUE or FALSE. When using handshaking on multiple port operations, use the highest numbered port CTL line to ensure correct data transfer.
Table 4-1.
Notes: 56 Understanding the Agilent E1330B Digital I/O Module Chapter 4
Chapter 5 Agilent E1330B Digital I/O Module Command Reference Using This Chapter This chapter describes Standard Commands for Programmable Instrumentation (SCPI) and summarizes IEEE 488.2 Common (*) Commands applicable to the Digital I/O Module. • Command Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • SCPI Command Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • IEEE 488.2 Common Commands . . . . . . . . . . . . . . . . . . . . . . . . .
Command Separator A colon (:) always separates one command from the next lower level command. This is illustrated as follows: MEASure:DIGital:DATAn:VALue? Colons separate the root command from the second level (MEASure:DIGital) and the second from third level (DIGital:DATAn), and so forth. Abbreviated Commands The command syntax shows most commands as a mixture of upper and lower case letters. The upper case letters indicate the abbreviated spelling for the command.
Parameters Parameter Types. The following table contains explanations and examples of parameter types you might see later in this chapter. Parameter Type Explanations and Examples Numeric Accepts all commonly used decimal representations of numbers including optional signs, decimal points, and scientific notation. 123, 123E2, -123, -1.23E2, .123, 1.23E-2, 1.23000E-01. Special cases include MIN, MAX, and DEF.
SCPI Command Reference This section describes the Standard Commands for Programmable Instruments (SCPI) commands for the Digital I/O Module. Commands are listed alphabetically by subsystem and within each subsystem.
DISPlay Subsystem The DISPlay subsystem turns on the Monitor mode. Monitor mode enables the Agilent E1301 Mainframe display, or an external terminal connected to either a B-size or a C-size mainframe. Parameters related to the state of the data and control lines are shown. Refer to the appropriate Command Module User's Guide (Agilent E1405/E1406) for supported terminal types.
:MONitor:PORT? DISPlay:MONitor:PORT? [], with no parameter, returns a decimal number indicating the port being monitored. If AUTO was selected as the port parameter in the DISP:MON:PORT AUTO command, the query returns a -1. If DEF is specified, the query always returns -1. If MAX is specified, the query returns the maximum port (always 3). If MIN is specified, the query returns the minimum port (always 0).
:MONitor[:STATe]? DISPlay:MONitor[:STATe]? returns a number indicating whether the monitor mode is enabled or disabled: 1 = ON, 0 = OFF. Parameters Chapter 5 None.
MEASure Subsystem The MEASure subsystem defines the command set for the Digital I/O Module input statements. Syntax MEASure :DIGital :DATAn [:BYTE] :BITm? :TRACe [:VALue]? :LWORd :BITm? :TRACe [:VALue]? :WORD :BITm? :TRACe [:VALue]? :FLAGn? :DIGital:DATAn[:type]:BITm? MEASure:DIGital:DATA n:BYTE:BITm? reads the state on bit m of 8-bit port n after the completion of the handshake.
• If n is omitted, bit 0 is used. • :BITm is the keyword that specifies the bit read by this command. Like the :DATA n keyword, no space can be between the keyword :BIT and the bit number m parameter. • Related Commands: [SOURce:]DIGital:DATAn:POLarity • *RST Condition: Set to input on all ports. Example MEAS:DIG:DATA2:BIT4? reads port 2, bit 4 (data line D2–4).
:DIGital:DATAn[:type][:VALue]? MEASure:DIGital:DATA n[:BYTE][:VALue]? reads one byte from 8-bit port n after the completion of the handshake and returns a decimal number between 0 and 255. MEASure:DIGital:DATA n:WORD[:VALue]? reads 2 bytes (one word) from 16-bit port n after the completion of the handshake and returns a decimal number between -32768 and 32767.
:DIGital:FLAGn? MEASure:DIGital:FLAGn? reads the status of the flag line on port n and returns a 0 or 1 to show whether a peripheral has set the flag line to READY or BUSY. Parameters Comments Parameter Name Parameter Type Range of Values Default FLAGn Numeric none, 0, 1, 2, or 3 0 • MEASure:DIGital:FLAGn? is used to implement custom handshakes. The handshake mode must be set to NONE to use these commands. • :FLAGn is the keyword used for commands relating to the flag line at port n.
MEMory Subsystem The MEMory subsystem defines the command set for enabling the use of external VME memory for storing traces and macros. The addressable range is #H200000 through #HDFFFF8 in A24 space. Syntax MEMory :DELete :MACRo :VME :ADDRess [] :ADDRess? [MIN |MAX] :SIZE [] :SIZE? [MIN |MAX] :STATe :STATe? :DELete:MACRo MEMory:DELete:MACRo deletes a single macro previously recorded using the *DMC common command.
:VME:ADDRess MEMory:VME:ADDRess []
establishes the address of add-on VME memory in the system which can then be used to store block data in commands with the :TRACe keyword. Parameters Comments Parameter Name Parameter Type Range of Values Default Discrete none, #H, #Q, or #B Decimal Numeric or Discrete 20000016–DFFFF8 16 None MIN or MAX • base specifies the numeric format as decimal, hexadecimal, octal, or binary. IEEE-488.:VME:SIZE MEMory:VME:SIZE [] sets the size, in bytes, of the external memory. Parameters Comments Parameter Name Parameter Type Range of Values Default Discrete none, #H, #Q, or #B Decimal Numeric or Discrete 00000016 - C00000 16 or MIN or MAX None None • Address plus size must not exceed #HE00000. • base specifies the numeric format as decimal, hexadecimal, octal, or binary. IEEE-488.
:VME:STATe MEMory:VME:STATe enables/disables the use of VME memory for storage. Parameters Comments Parameter Name Parameter Type Range of Values Default Value Boolean 0|1|ON|OFF 0|OFF • Related Commands: [SOURce:]DIGital:TRACe:DEFine, [SOURce:]DIGital:TRACe[:DATA], MEMory:VME:ADDress, MEMory:VME:SIZE • *RST Condition: Example Set to OFF. MEM:VME:STAT ON enables access to the VME memory. :VME:STATe? MEMory:VME:STATe? queries the state of the external memory.
[SOURce:] Subsystem The [SOURce:] subsystem defines the command set for the Digital I/O module output statements. It also defines the state and polarity of the control line (CTL), the polarity of the flag line (FLG), the handshaking mode, and handshake delay for both data input and output. The root command, [SOURce:], is optional.
[SOURce:] DIGital :DATAn :WORD :BITm <0| 1> :BITm? :HANDshake :DELay
DIGital:CONTroln:POLarity [SOURce:]DIGital:CONTroln:POLarity sets the CTL line voltage level for logical true in port n to either TTL high for POSitive polarity or TTL low for NEGative polarity. Parameters Comments Parameter Name Parameter Type Range of Values Default CONTroln Numeric none, 0, 1, 2, or 3 0 Discrete POSitive or NEGative None • Control lines are always accessed by their 8-bit port number.
DIGital:CONTroln[:VALue] [SOURce:]DIGital:CONTroln[:VALue] sets or clears the control line on the selected port n. Parameters Comments Parameter Name Parameter Type Range of Values Default CONTroln Numeric none, 0, 1, 2, or 3 0 Boolean 0 or 1, OFF or ON None • This command is used to create custom handshakes when the HANDshake is set to NONE. • :CONTroln is the keyword used for commands relating to the control (CTL) line at port n.
DIGital:DATAn[:type]:BITm [SOURce:]DIGital:DATAn[:BYTE]:BITm sets bit m on 8-bit port n. [SOURce:]DIGital:DATAn:WORD:BITm sets bit m on 16-bit port n. [SOURce:]DIGital:DATAn:LWORd:BITm sets bit m on 32-bit port n.
DIGital:DATAn[:type]:BITm? [SOURce:]DIGital:DATAn[:BYTE]:BITm? returns a 0 or 1 indicating the current programmed state of bit m on 8-bit port n. [SOURce:]DIGital:DATAn:WORD:BITm? returns a 0 or 1 indicating the current programmed state of bit m on 16-bit port n. [SOURce:]DIGital:DATAn:LWORd:BITm? returns a 0 or 1 indicating the current programmed state of bit m on 32-bit port n.
DIGital:DATAn[:type]:HANDshake:DELay [SOURce:]DIGital:DATAn[:BYTE]:HANDshake:DELay
DIGital:DATAn[:type]:HANDshake:DELay? [SOURce:]DIGital:DATAn[:BYTE]:HANDshake:DELay? queries for the delay time between data output and the control line for data output at 8-bit port n and returns a decimal number between 0 and .015. [SOURce:]DIGital:DATAn:WORD:HANDshake:DELay? queries for the delay time between data output and the control line for data output at 16-bit port n and returns a decimal number between 0 and .015.
DIGital:DATAn[:type]:HANDshake[:MODE] [SOURce:]DIGital:DATAn[:BYTE]:HANDshake[:MODE] selects the type of handshake and defines the timing relationship between the control (CTL) line, the flag (FLG) line, and when data is transferred in either direction between the Digital I/O Module and a peripheral on the 8-bit port n. [SOURce:]DIGital:DATAn:WORD:HANDshake[:MODE] selects the handshake mode used on the 16-bit port n.
DIGital:DATAn[:type]:HANDshake[:MODE]? [SOURce:]DIGital:DATAn[:BYTE]:HANDshake[:MODE]? returns a string indicating the type of handshake set on the 8-bit port n. [SOURce:]DIGital:DATAn:WORD:HANDshake[:MODE]? returns a string indicating the type of handshake set on the 16-bit port n. [SOURce:]DIGital:DATAn:LWORd:HANDshake[:MODE]? returns a string indicating the type of handshake set on the 32-bit port n.
DIGital:DATAn[:type]:POLarity [SOURce:]DIGital:DATAn[:BYTE]:POLarity sets the data line voltage level for logical true in the 8-bit port n to either TTL high for POSitive polarity or TTL low for NEGative polarity. [SOURce:]DIGital:DATAn:WORD:POLarity sets the data line voltage level for logical true in the 16-bit port n to either TTL high for POSitive polarity or TTL low for NEGative polarity.
DIGital:DATAn[:type]:TRACe [SOURce:]DIGital:DATAn[:BYTE]:TRACe writes the named block of data to 8-bit port n whenever the port is ready to start a new handshake. [SOURce:]DIGital:DATAn:WORD:TRACe writes the named block of data to 16-bit port n whenever the port is ready start a new handshake. [SOURce:]DIGital:DATAn:LWORd:TRACe writes the named block of data to 32-bit port n whenever the port is ready to start a new handshake.
DIGital:DATAn[:type][:VALue] [SOURce:]DIGital:DATAn[:BYTE][:VALue] [] writes data to 8-bit port n. Values can be binary, octal, decimal, or hexadecimal. [SOURce:]DIGital:DATAn:WORD[:VALue] [] writes data to 16-bit port n. Values can be binary, octal, decimal, or hexadecimal. [SOURce:]DIGital:DATAn:LWORd[:VALue] [] writes data to 32-bit port n. Values can be binary, octal, decimal, or hexadecimal.
DIGital:DATAn[:type][:VALue]? [SOURce:]DIGital:DATAn[:BYTE][:VALue]? returns the programmed state of 8-bit port n as a decimal number between 0 and 255. [SOURce:]DIGital:DATAn:WORD[:VALue]? returns the programmed state of 16-bit port n as a decimal number between -32768 and 32767. [SOURce:]DIGital:DATAn:LWORd[:VALue]? returns the programmed state of 32-bit port n as a decimal number between -231 and (231- 1).
DIGital:FLAGn:POLarity [SOURce:]DIGital:FLAGn:POLarity sets the voltage level for logical true to either TTL high, POSitive, or TTL low, NEGative on the FLG handshake line. Parameters Comments Parameter Name Parameter Type Range of Values Default FLAGn Numeric none, 0, 1, 2, or 3 0 Discrete POSitive or NEGative None • :FLAGn is the keyword used for commands relating to the flag line at port n. The port number n must be the last character of the keyword without spaces.
DIGital:HANDshaken:DELay [SOURce:]DIGital:HANDshaken:DELay
DIGital:HANDshaken:DELay? [SOURce:]DIGital:HANDshaken:DELay? queries for the time between data valid and the assertion of the control line to TRUE. This command operates on 8-bit ports and returns a decimal value between 0 and 0.015. Parameters Comments Parameter Name Parameter Type Range of Values Default HANDshaken Numeric None, 0, 1, 2, or 3 0 MIN|MAX|DEF Discrete None or MIN|MAX|DEF None • The delay time must be set to the same value on all ports used in a multiple port operation.
DIGital:HANDshaken[:MODE]? [SOURce:]DIGital:HANDshaken[:MODE]? returns a string indicating the current handshake mode of 8-bit port n. This form of the HANDshake command operates only on 8-bit ports. Parameters Comments Parameter Name Parameter Type Range of Values Default HANDshaken Numeric None, 0, 1, 2, or 3 0 • This command will return one of the following strings: NONE LEAD TRA PULS PART STR • :HANDshaken is the keyword used for commands relating to data handshaking at port n.
DIGital:TRACe:CATalog? [SOURce:]DIGital:TRACe:CATalog? lists the currently available data blocks. Parameters Comments None. • This command catalogs all blocks in VME memory and all blocks in the mainframe system memory. • The command returns a string. Example DIG:TRAC:CAT? would return this string if both alpha and beta had been previously defined; "alpha","beta". DIGital:TRACe[:DATA] [SOURce:]DIGital:TRACe[:DATA] , writes a block of data to a previously defined user memory block.
DIGital:TRACe[:DATA]? [SOURce:]DIGital:TRACe[:DATA]? reads a block of data from a previously defined user memory block. Parameters Comments Parameter Name Parameter Type Range of Values Default String Name of user memory block (maximum 12 characters) None • name must have been previously defined by a DIGital:TRACe:DEFine command. • The maximum length for name is 12 characters. Example DIG:TRACe? first_block reads data from a block named first_block.
DIGital:TRACe:DEFine? [SOURce:]DIGital:TRACe:DEFine? returns the size of a previously defined user memory block in bytes. The command returns a decimal number in the range of 0 to 12,582,912. Parameters Comments Parameter Name Parameter Type Range of Values Default String Name of user memory block (maximum 12 characters) None • must have been previously defined by a DIGital:TRACe:DEFine command. The maximum length for is 12 characters.
STATus Subsystem The STATus subsystem controls the SCPI-defined Operation and Questionable Signal Status Registers and the Standard Event Registers. Each is comprised of a Condition Register, an Event Register, an enable mask, and transition filters. Each Status Register works as follows: when a condition occurs, the appropriate bit in the Condition Register is set or cleared. If the corresponding transition filter is enabled for that bit, the same bit is set in the associated Event Register.
:OPERation:CONDition? STATus:OPERation:CONDition? returns the contents of the Operation Status Condition Register. Reading the register does not affect its contents. This command does not affect the Agilent E1330 Digital I/O module. :OPERation:ENABle STATus:OPERation:ENABle specifies which bits of the associated Event Register are included in its summary bit. The summary bit is the bit-for-bit logical AND of the Event Register and the unmasked bit(s).
:QUEStionable:CONDition? STATus:QUEStionable:CONDition? returns the contents of the Questionable Status Condition Register. Reading the register does not affect its contents. This command does not affect the Agilent E1330 Digital I/O module. :QUEStionable:ENABle STATus:QUEStionable:ENABle specifies which bits of the associated Event Register are included in its summary bit. The summary bit is the bit-for-bit logical AND of the Event Register and the unmasked bit(s).
SYSTem Subsystem The SYSTem subsystem returns information about the module. Syntax SYSTem :CDEScription? :CTYPe? :ERRor? :VERsion? :CDEScription? SYSTem:CDEScription? returns the module description. Parameters Comments Parameter Name Parameter Type Range of Values Default Numeric 1 None • This command is only available when using the downloaded SCPI driver. • is the instrument number.
:ERRor? SYSTem:ERRor? queries the Error Register for the error value and returns a string error message to identify the error type. The errors are held in an error buffer and read in a First-In-First-Out manner by this command. Comments • Returns the error number and error string. If no errors are in the error buffer, returns: +0,"No error". • Related Commands: *ERR • *RST Condition: None. Example SYST:ERR? queries the mainframe for errors.
IEEE 488.2 Common Commands The following table lists the IEEE 488.2 Common (*) Commands that can be executed by the Agilent E1330B Digital I/O Module. For more information on Common Commands, refer to ANSI/IEEE Standard 488.2-1987. Note These commands apply to many instruments and are not documented in detail here. See ANSI/IEEE Standard 488.2-1987 for more information. *IDN? Identification query Returns identification string of the Digital I/O Module.
Command Quick Reference The following tables summarize SCPI Commands for the Agilent E1330B Digital I/O module. Command DISPlay: MEASure: MEMory: Chapter 5 Description MONitor:PORT [AUTO |MIN|MAX|DEF] Sets the displayed monitor port number. MONitor:PORT? [] Returns the monitored port number. MONitor[:STATe] Turns the monitor mode of the display ON or OFF. MONitor[:STATe]? Returns the state of the monitor mode.
Command [SOURce:] 100 Description DIGital:CONTroln:POLarity Sets logical true level of control line on port n. DIGital:CONTroln:POLarity? Returns current logical true polarity of port n. DIGital:CONTroln[:VALue] <0|1 or ON|OFF> Sets or clears control line on port n. Command used to create custom handshakes when HANDshake is set to NONE. DIGital:CONTroln[:VALue]? Returns the current state of the control line on port n (downloaded SCPI driver only).
Command [SOURce:] (continued) STATus: Description DIGital:IOn? Returns the current state of the I/O control line on port n (downloaded SCPI driver only). DIGital:TRAce:CATalog? Returns the currently defined memory blocks. DIGital:TRAce[:DATA] , Writes a block of data to name . DIGital:TRAce[:DATA]? Reads a block of data from name. DIGital:TRAce:DEFine ,,[< fill>] Defines name, size, and initial fill for a memory block.
Notes: 102 Agilent E1330B Digital I/O Module Command Reference Chapter 5
Appendix A Agilent E1330B Digital I/O Specifications Logic Levels: TTL Compatible, 5V max Data Lines: Iout (High): -5.2 mA @ Vout (High): 2.5 V (Pull-up Enabled) Iout (Low): 48 mA @ Vout (Low): 0.5 V Vin (High): >2.0 V; <5.0 V Vin (Low): <0.8 V Iin (High): <2.5 mA @ 2.5 V Iin (Low): <-3.2 mA @ 0.4 V Handshake Lines: Iout (High): 250 µA @ Vout (High): 5 V Iout (Low): 40 mA @ Vout (Low): 0.7 V Iout (Low): 16 mA @ Vout (Low): 0.4 V Vin (High): >2.0 V Vin (Low): <0.8 V Iin (Low): <1.
Typical Data Line Current vs Data Line Voltage: Power Requirements: Voltage: +5 V Peak module current, IPM (A): 0.50 Dynamic module current, IDM (A): 0.01 Watts/Slot: 2.5 Cooling/Slot: 0.04 mm H 20 @ 0.21 liter/sec Humidity: 65%, 0º to 40 ºC Operating Temperature: 0º to 55ºC Storage Temperature: -40º to 75ºC EMC, RFI, Safety: meets FTZ 1046/1984, CSA 556B, IEC 348, UL 1244 Net Weight (kg): 1.
Appendix B Agilent E1330B Digital I/O Module Register Information Using This Appendix The contents of this appendix are: • Addressing the Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . • Reset and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • A Register-Based Output Algorithm. . . . . . . . .
The Base Address When you are reading or writing to a module register, a hexadecimal or decimal register address is specified. This address consists of a base address plus a register offset. The base address used in register-based programming depends on whether the A16 address space is outside or inside the Agilent E1405/06 Command Module.
A16 Address Space Inside the Command Module or Mainframe When the A16 address space is inside the Agilent E1405/06 Command Module (Figure B-2), the module's base address is computed as: 1FC00016 + (LADDR * 40)16 or 2,080,768 + (LADDR * 64) where 1FC00016 (2,080,768) is the starting location of the VXI A16 addresses, LADDR is the module's logical address, and 64 is the number of address bytes per register-based device. Again, the Agilent E1330's factory set logical address is 144.
Register Offset The register offset is the register's location in the block of 64 address bytes that belong to the module. For example, the module's Status/Control Register has an offset of 04 16.
Reset and Registers When the Digital I/O module undergoes a power on or *RST in SCPI, the bits of the registers are put into the following states: • The identification bytes at address 00 through 03, the Manufacturer ID and Device ID, remain unaffected. • The I/O bits (bit 6 of the Port Control/Status Registers (0-3)) are set to "1", enabling all four ports for input. • The port delay register is set to 2 µs. • The port handshake register is set to interrupt driver.
The module is a register-based slave/interrupter device, supporting VME D16, D8(O), and D8(OE) transfers. The interrupt protocol supported is “release on interrupt acknowledge” – an interrupt is cleared by a VXIbus interrupt acknowledge cycle. WARNING 110 Registers have been documented as 8 bit bytes. If you access them using 16 bit transfers from a Motorola CPU, the high and low byte will be swapped. The Agilent E1300/01 Mainframe and Agilent E1405/06 Command Modules use Motorola CPUs.
Register Descriptions The following pages detail register descriptions of the Digital I/O module. Manufacturer Identification Register The Manufacturer Identification Register is a read-only register at address 0016 (Most Significant Byte (MSB)) and 0116 (Least Significant Byte (LSB)). Reading this register returns the Agilent Technologies identification, FFFF16. Device Identification Register The Device Identification Register is a read-only register accessed at address 0216.
Port Interrupt Control Register The Port Interrupt Control Register is a read/write register and functions as the interrupt register for the port. This register shows the interrupt enable status, the level of interrupt that can signal the controller (always set to 0), and whether an interrupt is pending. Port Address (0–3) base+0816 , base+0916, base+0A16, base+0B 16 Bits (0-3) IL0 and IL1 (Interrupt Level) 7 6 5 4 3 2 1 0 PIEN IP IL1 IL0 — — — — Are unused.
Port Transfer Control Register The Port Transfer Control Register controls transfers between the mainframe and port, identifies port interrupts, and identifies forced interrupts from the controller. Port Address (0–3) base+0C16, base+0D16, base+0E16 , base+0F16 7 6 5 4 3 2 1 0 PI FI TI — — — HE DRR DRR (Data Register Ready) Is a read-only bit.
Port Control/ Status Register The Port Control/Status Register shows the status of STS, PIR, and FLG lines. It also directly controls the RES, I/O and CTL lines. Port Address (0–3) base+1016, base+1116, base+1216, base+1316 7 6 5 4 3 2 1 0 CTL I/O RES FLG — — PIR STS STS Bit 0 is read-only bit. Read this bit to find the status of the STS line, which is an input from the peripheral for the port. A "1" shows that the line is BUSY; a "0", shows that the line is READY.
I/O This is a read/write bit. Read this bit to find the current status of the I/O line, which is an output line to the peripheral, and the port data transceiver. If bit 6 is equal to "0", the line is FALSE and the transceiver is enabled for output. If bit 6 is equal to "1", the line is TRUE and the transceiver is enabled for input. This bit is equal to "1" (input) after a hardware reset. You can select input or output by changing this bit.
Port Handshake Register The Port Handshake Register determines the type of handshake protocol used for the port data transfers and how the data is transferred from the Digital I/O module to the mainframe on the VXIbus. Port Address (0–3) TM(0,1) (Transfer Mode) base+1816, base+1916, base+1A16 , base+1B16 7 6 5 4 3 2 1 0 HT2 HT1 HT0 EI — — TM1 TM0 These bits control the transfer mode for the port between the Digital I/O module and the VXIbus as shown in Table B-3. Table B-3.
Table B-4. Handshake Type Port Delay Register Output/Input Transfer Bit 7 Bit 6 Bit 5 No Handshake (NONE) 0 0 0 LEADing Edge 0 0 1 TRAiling Edge 0 1 0 PULSe 0 1 1 PARTial 1 0 0 STRobe 1 0 1 The Port Delay Register sets the delay time, T d. Delay time is the time between data valid and setting the control (CTL) line TRUE. It is used with several handshake modes. You can also read this register to find the current delay time.
Note If you are using the output STRobe or PULSe handshake, you can specify delay factors in the range 2 through 15, or you can specify 0 (no delay period). Thus, you can specify T d values from 2 to 15µs, from 20 to 150µs, and so forth for these handshakes. If you are using the input STRobe handshake, the delay factor specified by bits 4 through 7 is reduced by one, then multiplied by the range multiplier. For example, the register value "00100000" for an input STRobe handshake specifies T d = 1 ms.
A Register-Based Output Algorithm The following algorithm describes the procedure you would use to program the registers to transmit a byte of data to a peripheral. The algorithm follows a flag-driven output procedure initiated by the computer. The computer polls the Digital I/O module to see if the data has been accepted by the peripheral by checking the Port Transfer/Control Register, bit 0 (referred to as the acknowledge flag - hence, the name of flag-driven).
A Register-Based Input Algorithm The following algorithm describes the procedure you use to program the registers to read a byte of data from a peripheral. The algorithm follows a flag-driven input procedure initiated by the computer. The computer polls the Digital I/O module to see if the data has been transmitted by the peripheral by checking the Port Transfer/Control Register, bit 0 (referred to as the acknowledge flag - hence, the name flag-driven).
Programming Examples The examples in this section demonstrate how to program the module at the register level. The programs follow the execution and timing models covered in the previous section.
Resetting the Module IBASIC Version C Version The following program resets the Agilent E1330 Digital I/O module (Bit 6 of the Port Control/Status Register set to "1" then to"0"). Reset enables all four ports for input, all other bits of other registers set to "0" IBASIC Version. 10 20 30 40 50 60 Base_addr = DVAL("1FE400",16) !Logical Address 144. Reg_addr = 04 !Offset for Status Control Register. !Write a 0 then a 1 to bit 0 of status register.
Reading the ID, Device Type, and Status Registers The following examples read the module ID, DEVICE ID, and STATUS registers from the module.
C Version #include #include #include
Writing an 8-Bit Byte IBASIC Version Appendix B Using the output algorithm described earlier, the following programs describe how to output an 8-bit byte to your peripheral device. The program use a leading edge handshake and flag-driven data transfer to send data (decimal value 255) from Port 1. 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 Base_addr = DVAL("1FE400",16) !Logical Address 144.
C Version 126 /* writing an 8-bit byte */ #include #include
Writing a 16-Bit Word Similar to the last program example, this program outputs a 16-bit word to your peripheral device. To write a 16-bit word, two consecutive ports are required (i.e. ports 0 and 1, 1 and 2, 2 and 3, or 3 and 4). Both ports must be configured exactly the same. Configure consecutive port registers by addressing the lower port's register and sending a 16-bit word. Handshaking is accomplished using the lower port's handshake lines.
Reading an 8-Bit Byte BASIC Version 128 Using the input algorithm described earlier, the following programs describe how to input an 8-bit byte from your peripheral device. The program use a leading edge handshake and flag-driven data transfer. 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 Base_addr = DVAL("1FE400",16) !Logical Address 144. WRITEIO 9826,Base_Addr+DVAL("19",16);32 !Set Port 1 Handshake Register to leading edge handshake and flag !driven transfer.
C Version /* reading an 8-bit byte */ #include #include
IOEOI (7L, 0); IOEOL (7L, " ", 0); IOOUTPUTS (70900L, "DIAG:POKE ", 10); IOEOI (7L, 1); IOEOL (7L, state, 0); IOOUTPUTA (70900L, send_data, 3); } Reading a 16-Bit Word Debugging Basic RegisterBased Programs To read a 16-bit word, two consecutive ports are required (i.e. ports 0 and 1, 1 and 2, 2 and 3, or 3 and 4). Both ports must be configured exactly the same. Configuring consecutive port registers by addressing the lower port's register and sending a 16-bit word.
When debugging, it is often necessary to go between editing and running of the program. To accelerate this activity it is very helpful to assign a line label to the first line of a subprogram that is the same as the subprogram name. This makes it possible to start editing by typing EDIT . PIR Interrupts on the Agilent E1330 This example demonstrates how to use the four PIR interrupt lines that exist on the Agilent E1330A/B digital I/O module.
2. Re-enables the System Instrument features that catch the backplane interrupt and pull the bus SRQ. i.e. 960 980 990 1010 1020 1220 A=SPOLL(@Sys) OUTPUT @Sys;"STAT:OPER:EVEN?" ENTER @Sys;Stat_oper OUTPUT @Sys;"DIAG:INT:RESP?" ENTER @Sys;Int_ack OUTPUT @Sys;"DIAG:INT:SETUP2 ON; :DIAG:INT:ACT ON" 3. Re-enable the BASIC Language interrupt features that catch the bus SRQ. i.e. 1240 ENABLE INTR 7;2 This program has been written to run on an external computer connected via GPIB to the Agilent E1300/01.
150 160 170 180 190 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 360 370 380 390 400 410 420 430 440 450 460 470 480 490 500 510 520 530 540 550 560 570 580 590 600 610 620 630 640 650 660 Appendix B ! Main !Put application code in this sub.
670 END LOOP 680 Main_:SUBEND 690 ! 700 SUB Reset_dig 710 COM /Register/ Logical_address 720 COM /Instr/ @Sys,@Dig 730 OUTPUT @Dig;"*RST;*OPC?" !May use SCPI as reset does not use interrupts as the IRQ2 jumper is being used. 740 ENTER @Dig;A 750 SUBEND 760 Reg_dump:SUB Reg_dump 770 !This queries all E1330 registers to help debugging.
1150 Enable_pir2 1160 END IF 1170 IF BIT(Int_ack,10)=0 THEN 1180 PRINT "PIR3 OCCURRED" 1190 Enable_pir3 1200 END IF 1210 Enable_int 1220 OUTPUT @Sys;"DIAG:INT:SETUP2 ON;:DIAG:INT:ACT ON;*OPC?" 1230 ENTER @Sys;A 1240 ENABLE INTR 7;2 1250 Int_ser_:SUBEND 1260 ! 1270 Res0_1:SUB Res0_1 !Subprogram to drive line RESO (PIN 5) to 1. 1280 ! !Must have a pullup on RES0 as it is open collector.
1630 1640 1650 1660 COM /Instr/ @Sys,@Dig COM /Register/ Logical_address Base=2031616+49152+(Logical_address*64) OUTPUT @Sys;"DIAG:POKE "&VAL$(Base+(DVAL("0E",16)))&",8,0" ! PI=0 1670 OUTPUT @Sys;"DIAG:POKE "&VAL$(Base+(DVAL("0A",16)))&",8,128" !PIEN=1 1680 OUTPUT @Sys;"DIAG:POKE "&VAL$(Base+(DVAL("0E",16)))&",8,128" ! PI=1 1690 Enable_pir2_:SUBEND 1700 ! 1710 Enable_pir3:SUB Enable_pir3 1720 COM /Instr/ @Sys,@Dig 1730 COM /Register/ Logical_address 1740 Base=2031616+49152+(Logical_address*64) 1750 OUTPUT
10 20 30 40 50 60 70 80 90 !re-save "DIG_NDL". !Program to demonstrate the non-data lines—FLAG/CONTROL,RES/STS, PIR. !This main line code is reserved as a error handling shell. !All application code must be at lower level context. ASSIGN @Sys TO 70900 !Define I/O paths. ASSIGN @Dvm TO 70903 ASSIGN @Dig TO 70910 COM @Sys,@Dvm,@Dig ON TIMEOUT 7,3 GOTO End !Turn TIMEOUTS to errors—this branch never taken. 100 ON ERROR RECOVER Kaboom !This handles timeouts and errors not handled. 110 !at lower level contexts.
540 550 560 SUBEND ! SUB Cnt_flg_io 570 580 590 600 610 !Demonstrates driving CONTROL0 then receiving Flag 0. !Connect CONTROL 0 to FLAG 0. COM @Sys,@Dvm,@Dig PRINT “” PRINT “SUBPROGRAM Cnt_flg_io” OUTPUT @Dig;"*RST" !RESET to power on state. OUTPUT @Dig;"SOUR:DIG:CONT0:VAL 0" !Drive CONTROL 0 to 0. 620 OUTPUT @Dig;"MEAS:DIG:FLAG0?" !Read FLAG 0. 630 ENTER @Dig;A 640 PRINT “CONTROL0 DRIVEN TO 0 AND FLAG0 RECEIVED AS ”;A 650 OUTPUT @Dig;"SOUR:DIG:CONT0:VAL 1" !Drive CONTROL 0 to 1.
1020 1030 1040 1050 1060 1070 1080 1090 1100 1110 1120 1130 1140 1150 1160 1170 1180 1190 1200 1210 1220 1230 1240 1270 1280 1290 1300 1310 1320 1330 1340 1350 1360 1370 1380 1390 1400 1410 1420 1430 1440 1450 1460 1470 Appendix B OUTPUT @Sys;"DIAG:POKE "&VAL$(Base+(DVAL("10",16))) &",8,64" !Drive RES0 to 0. OUTPUT @Sys;"DIAG:PEEK? "&VAL$(Base+(DVAL("10",16))) &",8" !Read REG B+10H.
Embedded Computer Example The following example was developed with the module at logical address 144. The C language programs were developed on an Agilent V382 using ANSI C programming language and SICL (Standard Instrument Control Library). /* C register programming example */ #include #include #include
test_1 = 0; /* port is ready */ else test_1 = 1; /* port not ready */ return test_1; } main () { INST id; unsigned short data_word; unsigned char data_byte; int reg_num; char *base_addr; int errnum; /* open a path to digital I/O module */ id = iopen("vxi,144"); if (id == 0){ errnum = igeterrno(); printf ("iopen failed: error = %d,%s\n\n",errnum,igeterrstr(errnum)); exit (-1); } /* get base address */ base_addr = imap(id,I_MAP_VXIDEV,0,0,NULL); if (base_addr == NULL){ errnum = igeterrno(); printf("imap failu
/* port 3 */ ibpoke((base_addr + port_hand_1),0x00); ibpoke((base_addr + port_del_1),0x00); ibpoke((base_addr + port_norm_1),0x00); ibpoke((base_addr + port_ctl_1),0x00); ibpoke((base_addr + port_xfr_1),0x00); ibpoke((base_addr + port_data_1),pattern_2); /* return ports back to input state */ ibpoke((base_addr + port_ctl_0),0x40); ibpoke((base_addr + port_xfr_0),0x00); ibpoke((base_addr + port_ctl_1),0x40); ibpoke((base_addr + port_xfr_0),0x00); /* input a data byte at port 2, no handshake */ ibpoke((base_a
Appendix C Error Messages Code Message Cause -101 Invalid character Unrecognized character in specified parameter. -102 Syntax Error Command is missing a space or comma between parameters. -103 Invalid separator Command parameters are not separated by a comma. -104 Data Type Error The wrong data type (i.e. number, character, string, expression) was used when specifying a parameter. -108 Parameter not allowed Parameter specified in a command where none is allowed.
Notes: 144 Error Messages Appendix C
Index Agilent E1330B User’s Manual Symbols *CLS, 98 *DMC , 68, 98 *EMC , 98 *EMC?, 98 *ESE , 98 *ESE?, 98 *ESR?, 98 *GMC , 98 *IDN , 98 *LMC , 98 *OPC, 98 *OPC?, 98 *PMC, 68, 98 *RCL, 98 *RMC, 98 *RST, 33, 43, 98 *SAV, 98 *SRE, 98 *SRE?, 98 *STB?, 98 *TRG, 98 *TST?, 98 *WAI, 98 A A16 Address Space , 105–107 inside the command module, 107 inside the mainframe, 107 outside the command module, 106–107 A24 Address Space , 68 Abbreviated Commands , 58 Address base, 106–107 GPIB, 31 LADDR, 18 , 31 logical switc
C C Program Examples reading an 8-bit byte, 129 registers , 124 resetting the module, 122 using an embedded computer, 140 writing a 16-bit word, 127 an 8-bit byte, 126 Cables digital I/O, connecting , 24 ribbon cable data line location , 24 ordering , 12 Card Edge Connector, 25 Card Status/Control Register, 111 *CLS, 98 Combining Flag Lines , 21 Command Parameters, rules for use, 14, 59 Command Reference, 57–101 abbreviated commands , 58 command quick reference, 99–101 separator, 58 types, 57 common command
C (continued) Control Lines CTL , 12, 21–22, 42, 115, 136 FLG, 12, 16, 21–22, 42, 114, 136 I/O, 12, 22, 42, 89, 115 PIR , 12, 22 , 43, 114 , 136 polarity, 33, 43, 74 RES, 12, 22, 43, 114, 136 setting value, 75 specify logic sense, 118 STS, 12, 22, 43, 114, 136 CTL Control Line, 12, 21–22 clearing value , 75 controlling, 114 default/reset state, 33, 43 description , 42 for handshaking , 21 input/output handshaking, 54 invert CTL, 118 operation, 42 operation of, 115 polarity, 33, 43 setting polarity, 33, 42–4
F Flag Control Line See FLG Control Line Flag Line polarity, 86 query status, 67 specify logic sense, 118 FLG Control Line, 12, 22 combining, 21 description , 42 factory setting , 21 input/output handshaking, 54 invert FLG, 118 operation, 42 operation of, 114 polarity, 33, 43, 86 setting polarity, 16, 33, 42–43, 86 status , 114 using as input lines , 136 Format common commands, 57 output, 52 SCPI commands , 57–59 Function Reference (VXIplug&play) See online help G Getting Started , 11–14, 16 *GMC , 98 GPIO
I (continued) Internal Pull-up, 19, 29 Interrupts disable, 20 flags, 111 line, 20 peripheral, 114 PIR control line, 131 setting priority, 20 VXIbus, 20, 110 J Jumpers flag combining , 67 hardware configuration , 12 interrupt line, 20, 132 JM15 and JM16 , 20 pull-up enable, 19 K Keyword rules for use, 58 substitutions , 59 L LADDR, 18, 31 LEADing Edge Handshake Mode, 34, 44–45, 80–81, 88–89, 117 Linking Commands, 59 *LMC , 98 Logical Address , 18, 31 changing, 18, 31 factory setting , 18, 31 , 107 switch
M (continued) Multiple port handshaking , 53 input/output, 54 operations, 37 , 53 ports single handshake line, 21 specifying, 15 , 37, 53 SCPI commands, linking , 59 N Non-Data Line I/O , 136 NONE Handshake Mode, 34, 44, 49, 80–81, 88–89, 117 Numeric Command Parameters , 59 O Octal Format, 52, 54 *OPC, 98 *OPC?, 98 Open Collector configuration, 28 –29 data lines , 29 Operation flowchart , 32 overview, 32 Operation Event Status Register, 94 Operation Status condition register, 94 enable register, 94 event
P (continued) Ports (continued) peripheral interrupt request (PIR) line, 43 reset (RES) line, 43 specifying, 14 specifying multiple, 15, 37, 53 status (STS) line, 43 transfer control register, 113 transfer mode, 116 type combinations allowed , 55 writing data to, 83–84 Primary Address, 31 Program Examples combine all 4 ports , 37 input data bits and bytes , 35 output data bits and bytes, 36 reading an 8-bit byte, 128–129 registers , 123–124 register access, 121 resetting the module, 122 set the handshake mo
R (continued) Register-Based debugging programs, 130 input algorithm, 120 output algorithm, 119 programming examples, 121 Registers addressing, 105 –110 base address , 106–107 card status/control, 111 condition register, 93–95 definitions, 109 –110 descriptions , 111–118 Device Identification Register, 111 event register, 93–95 information , 105–142 manufacturer ID , 111 map, 109 –110 offset , 108 operation event status , 94 operation status condition register, 94 enable register, 94 event register, 94 regi
S (continued) Setting (continued) handshake mode, 34, 44–49, 80, 88 interrupt line, 20 polarity, 33, 41, 43, 74, 82 VME external memory, 70 Soft [SOURce:]Front Panel (VXIplug&play) See online help SOURce Subsystem, 72–92 [SOURce:]DIGital:CONTroln :POLarity, 33 , 43, 74 :POLarity?, 74 [:VALue], 75 [:VALue]?, 75 [SOURce:]DIGital:DATAn [:BYTE]BITm, 76 [:BYTE]BITm?, 77 [:BYTE]HANDshake:DELay, 78 [:BYTE]HANDshake:DELay?, 79 [:BYTE]HANDshake[:MODE], 80 [:BYTE]HANDshake[:MODE]?, 81 [:BYTE]POLarity, 82 [:BYTE]POLar
S (continued) STATus:PRESet , 94 STATus:QUEStionable:CONDition?, 95 STATus:QUEStionable:ENABle, 95 STATus:QUEStionable:ENABle?, 95 STATus:QUEStionable[:EVENt]?, 95 *STB?, 98 STRobe Handshake Mode, 34, 44, 49, 78, 80–81, 87–89, 117 STS Control Line, 12, 22 description , 43 operation, 43 operation of, 114 status , 114 using as input lines , 136 Summary Bit , 93–95 Switches flag combining , 21 logical address , 18, 31 System Configuration , 121 SYSTem Subsystem, 96–97 SYSTem:CDEScription?, 96 SYSTem:CTYPe?, 9
