Technical data

DisplayPort Source Automated Test with W2642A DPTC A
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application 241
2 Once a 1ms HPD pulse is received:
a Source reads bit 0x201.1 (AUTOMATED_TEST_REQUEST). If 0x201.1
is asserted, go to step 2
b If 0x218.3 is asserted, source clears TRANING_LANE[X,Y]_SET,
TRAININ_PATTERN_SET:LINK_QUAL_PATTERN_SET
c Source reads 0x248,0x206,0x207 and outputs signals with the desired
pattern, Pre- Emphasis and level
d Source updates TRANING_LANE[X,Y]_SET,
TRAININ_PATTERN_SET:LINK_QUAL_PATTERN_SET
e If successful, source clears bit 218.3
f If the test request is successful, sink checks
TRANING_LANE[X,Y]_SET,
TRAININ_PATTERN_SET:LINK_QUAL_PATTERN_SET
OPTION 2
This option provides an easier way to control the test automation in one
simple step. However, it is less consistent with the DisplayPort Automation
scheme.
Step 1:
1 Source should always scan for 0x201.1 (AUTOMATED_TEST_REQUEST).
2 Sink sets the following:
a Set byte 0x219 (TEST_LINK_RATE) to 0x0A(2.7 Gbps) or 0x06(1.62
Gbps)
b Set bit 0x03.1(TEST_DOWNSPREAD) to turn on SSC. Clear 0x21A.1
to turn off SSC
c Set byte 0x220 (TEST_LANE_COUNT) to desired lane count
d Set 0x206 (ADJUST_REQUEST_LANE0_1) and 0x207
(ADJUST_REQUEST_LANE2_3) with desired level and preemphasis
e Set 0x248(PHY_TEST_PATTERN) to desired pattern
3 Sink sets 0x201.1.
4 Once source detects 0x201.1 being set, it outputs signals as in step 2, as
a response.
5 Source sets bit 0x218.0 to indicate that the operation is completed.
6 Sink sets bit 0x218.0 back to 0.
7 Alternatively, HPD_IRQ(1ms) mechanism could be used instead of
scanning 0x201.1