Technical data

236 Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
A DisplayPort Source Automated Test with W2642A DPTC
Automated Test Sequence
This section provides information on how to enable the test automation in
DisplayPort Source test. You should specify the max link rate, lane count,
preEmphasis, Level and SSC option in the compliance application.
OPTION 1
Step 1: Emulate successful link training (For SSC)
1 This step emulates a fake link training to cheat the source that a sink
device is connected.
2 To do this, the DPTC controller initiates the sequence as below:
a Emulate PlugOut Event to put HPD line in Low for at least 2ms.
Source should RESET
b Set Link Capability fields as below:
• MAX_LINK_RATE =0x0A
• MAX_LANE_COUNT = 0x04
• MAX_DOWNSPREAD = 0x01 to enable SSC / 0x00 to disable SSC
c Set 0x202 (LANE0_1_STATUS) = 0x77
d Set 0x203 (LANE2_3_STATUS) = 0x77
e Set 0x204 (LANE_ALIGN__STATUS_UPDATED) = 0x81
f Emulate PlugIn Event to put HPD line in High
g Source clears Link Configuration field and reads Link Capability
h Source enables or disables SSC based on the value of
MAX_DOWNSPREAD (Enable SSC if value is 1) and writes to
DOWNS_SPREAD_CTRL. Source writes LINK_BW_SET,
TRANING_LANE[X,Y]_SET, LANE_COUNT_SET based on default
settings
i Source outputs 0x01 to TRAINING_PATTERN_SET
j Source reads LANE0_1_STATUS, LANE2_3_STATUS and
LANE_ALIGN__STATUS_UPDATED. Since these registers are already
set in step 3- 5, source exits the Clock Recovery Sequence of Link
Training (
Figure 100) and go to Channel Equalizer sequence for Link
Training (Figure 101).
k Source sets TRAINING_PATTERN_SET to 0x02.
l Source reads LANE0_1_STATUS, LANE2_3_STATUS and
LANE_ALIGN__STATUS_UPDATED. Since these registers are already
set in step 3- 5, source exits Channel Equalizer sequence and ends
the entire link training process.