Technical data

118 Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
13 Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative)
SSC Modulation Frequency Test Condition
Bit Rate: highest rates are supported.
Output Level: 800 mVolts.
Pre- Emphasis: 0 dB.
Test Pattern: D10.2.
SSC: Enabled. The devices that do not have SSC Enabled will not be
tested.
An evaluation of at least 10 full SSC cycle is required.
SSC Modulation Deviation Test Condition
Bit Rate: highest rates are supported.
Output Level: 800 mVolts.
Pre- Emphasis: 0 dB.
Vswing Edge Sets the number of Edges used when performing the Vswing
measurement. The Vswing value is used to ensure that the waveform
is displayed as large as possible in the waveform viewing area.
Increasing this value increases the test run time but improves the
repeatability of the measurement.
VTop & VBase Edge Sets the number of edges required when making the VTop and VBase
measurements.
Expert Mode Turn on the expert mode for looser pre-requisite checker.
Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth Sets the memory depth for acquisition
PRBS Validation Algorithm Settings
PRBS pattern checker
rule
Determine the rules applied to PRBS 7 Pattern detector. By selecting
Strict, test can only proceed with the correct PRBS 7 pattern only.
Table 15 Test Configuration Options
Configuration Option Description