Technical data

Source Main Link Frequency Compliance Differential Tests 12
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application 109
Test Condition
Bit Rate: all bit rates are supported.
Output Level: 800 mVolts.
Pre- Emphasis: 0 dB.
Test Pattern: D10.2.
SSC: If the device under test is able to operate either with SSC Enabled or
SSC Disabled then the device is tested for both conditions. If the device is
always SSC Enabled or always SSC Disabled then the device is tested in
its normal state.
An evaluation of at least 10 full SSC cycles are required.
PASS Condition
The Main Link Frequency Compliance Test result must satisfy the
following criteria:
SSC frequency
ppm
≤ 300.
Test R ef er en ce s
See Test 3.14: Main Link Frequency Compliance Tests, in the
DisplayPort- Compliance Test Specification Version 1.1.
Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth Sets the memory depth for acquisition
PRBS Validation Algorithm Settings
PRBS pattern checker
rule
Determine the rules applied to PRBS 7 Pattern detector. By selecting
Strict, test can only proceed with the correct PRBS 7 pattern only.
Table 14 Test Configuration Options
Configuration Option Description