User`s manual

• Status Register. Reading this 16-bit register provides information
about the status of the breadboard module. Implemented signals are
"A24/A32 Active", "MODID*", "Extended*" and "Passed". There
are also provisions for implementing device-dependent status bits.
See page 36 for information about the Status Register.
• ID Register. Reading this 16-bit register identifies the manufacturer
identification number, the device class, and the addressing mode of
the breadboard. By using the DIP switches, the user selects
hardwired configurations for these items. See page 37 for
information about the ID Register.
• Device Type Register. Reading this 16-bit register identifies the
unique card model as defined by the device manufacturer. It also
indicates the amount of memory available on the card in bytes (for
A24 and A32 devices only). By using the DIP switches, the user
selects hardwired configurations for these items. See page 38 for
information about the Device Type Register.
• Control Register. Writing to this 16-bit register causes specific
actions to be executed by the device. "Reset" and "System Fail
Inhibit" are implemented. Other device-dependent control bits may
be implemented by using the remaining device dependent bits. See
page 40 for information about the Control Register.
• Read/Write Operations. Using the backplane interface circuitry
provided, it is possible to read the contents of the Status, ID, or Device
Type Registers onto the data bus (D0 - D15), or to write information
into the Control Register from the data bus. See pages 51 - 54 for
information about reading from and writing to the registers.
• DTACK. The interface contains the circuitry required for generating a
delayed DTACK* (data transfer acknowledge) signal. See page 41 for
information about data transfer acknowledge (DTACK) circuitry.
• Interrupt Interface. The breadboard module has D16 interrupter
capability. It does not contain an interrupt handler. Interrupt
priority is jumper-selectable for pulling the appropriate interrupt
request line IRQ1* - IRQ7*. Interrupts are generated by the IRQ
state machine on the DTACK interrupt control IC. The
daisy-chained IACKIN*/IACKOUT* signal pair is implemented.
See pages 43 and 57 for information about interrupt circuitry.
• Module Reset. Both hardware and software reset signals are
provided to initialize the backplane interface circuitry and your own
custom-designed circuitry to a known state. See page 59 for
information about resetting the module.
• Backplane Buffering. Buffering is provided for all signals that
interface with the VXIbus backplane. See page 32 for information
about backplane interface circuitry.
• Power Supply. + 5 Vdc from the backplane is fused at 4 A and
filtered for use on the module. The - 5.2 Vdc is also filtered. Other
backplane voltages are available. See pages 47 and 60 for
information about power supplies.
10 Introduction Chapter 1