Technical data

Introduction to SCPI 1
U2761A Programmer’s Reference 15
Status Byte register
The Status Byte register group reports the conditions from the other
status registers. Clearing an event register from one of the other registers
will clear the corresponding bits in the Status Byte condition register.
Data that is waiting in the U2761A output buffer is immediately reported
on the “Message Available” bit (bit 4).
Bit definitions: Status Byte register
The Status Byte condition register will be cleared when:
• you execute the clear status (*CLS) command
• you read the event register from one of the other register groups, only
the corresponding bits are cleared in the condition register
The Status Byte enable register is cleared when you execute the *SRE 0
command.
Bit number Decimal
value
Definition
0 to 1 Not Used Not Used 0 is returned
2 Error Queue 4 There is at least one error message in the error queue
3 Questionable Data Summary 8 One or more bits are set in the Questionable Data register (bits
must be enabled in the enable register)
4 Message Available 16 Data is available in the U2761A output buffer
5 Event Status Byte Summary 32 One or more bits are set in the Standard Event register (bits must
be enabled in the enable register)
6 Master Status Summary
(Request for Service)
64 One or more bits are set in the Status Byte register (bits must be
enabled in the enable register). Also used to indicate a request for
service.
7 Not Used Not Used 0 is returned
NOTE
Refer to Chapter 2, “IEEE-488.2 Common Commands” on page 17 for details of the common
IEEE commands mentioned above.