User's Manual
Table Of Contents
- Agilent Technologies 16750A/B Logic Analyzer
- Agilent Technologies 16750A/B Logic Analyzer
- Contents
- Getting Started
- Step 1. Connect the logic analyzer to the device under test
- Step 2. Choose the sampling mode
- Step 3. Format labels for the probed signals
- Step 4. Define the trigger condition
- Step 5. Run the measurement
- Step 6. Display the captured data
- For More Information...
- Example: Timing measurement on counter board
- Example: State measurement on counter board
- Task Guide
- Probing the Device Under Test
- Choosing the Sampling Mode
- To select transitional timing or store qualified
- Formatting Labels for Logic Analyzer Probes
- Setting Up Triggers and Running Measurements
- Displaying Captured Data
- Using Symbols
- Printing/Exporting Captured Data
- Cross-Triggering
- Solving Logic Analysis Problems
- Saving and Loading Logic Analyzer Configurations
- Reference
- The Sampling Tab
- The Format Tab
- Importing Netlist and ASCII Files
- The Trigger Tab
- The Symbols Tab
- Error Messages
- Must assign Pod 1 on the master card to specify actions for flags
- Branch expression is too complex
- Cannot specify range on label with clock bits that span pod pairs
- Counter value checked as an event, but no increment action specified
- Goto action specifies an undefined level
- Maximum of 32 Channels Per Label
- Hardware Initialization Failed
- Must assign another pod pair to specify actions for flags
- No more Edge/Glitch resources available for this pod pair
- No more Pattern resources available for this pod pair
- No Trigger action found in the trace specification
- Slow or Missing Clock
- Timer value checked as an event, but no start action specified
- Trigger function initialization failure
- Trigger inhibited during timing prestore
- Trigger Specification is too complex
- Waiting for Trigger
- Analyzer armed from another module contains no "Arm in from IMB" event
- Specifications and Characteristics
- Concepts
- Understanding Logic Analyzer Triggering
- Understanding State Mode Sampling Positions
- Getting Started
- Glossary
- Index

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Chapter 2: Task Guide
Displaying Captured Data
If the captured data doesn't look correct
Intermittent Data
Errors
Check for poor connections, incorrect signal levels on the hardware,
incorrect logic levels under the logic analyzer's Config tab, or marginal
timing for signals.
Unwanted Triggers
If you are using an inverse assembler or a pipeline, triggers can be
caused by instructions that were fetched but not executed. To fix, add
the prefetch queue or pipeline depth to the trigger address.
The depth of the prefetch queue depends on the processor that you are
analyzing, and can be quite deep.
Another solution which is sometimes preferred with very deep prefetch
queues is to add writes to dummy variables to your software. Put the
instruction just before the area you want to trigger on, then trigger on
the actual write to this variable. Although the instruction is prefetched,
the analyzer can be set to only trigger when the write is executed.
Capacitive Loading on
the Device Under Test
Excessive capacitive loading can degrade signals, resulting in
suspicious data or even system lockup. All analysis probes add
capacitive loading, as can custom probes you design for your device
under test. To reduce loading, remove as many pin protectors,
extenders, and adapters as possible.
Careful layout of your device under test can minimize loading problems
and result in better margins for your design. This is especially
important for systems running at frequencies greater than 50 MHz.
If there are filtered data holes in display
memory
When an analyzer measurement occurs, acquisition memory is filled
with data that is then transferred to the display memory of the analysis
or display tools you are using, as needed by those tools. In normal use,
this demand driven data approach saves time by not transferring
unnecessary data.