User's Manual
Table Of Contents
- Agilent Technologies 16750A/B Logic Analyzer
- Agilent Technologies 16750A/B Logic Analyzer
- Contents
- Getting Started
- Step 1. Connect the logic analyzer to the device under test
- Step 2. Choose the sampling mode
- Step 3. Format labels for the probed signals
- Step 4. Define the trigger condition
- Step 5. Run the measurement
- Step 6. Display the captured data
- For More Information...
- Example: Timing measurement on counter board
- Example: State measurement on counter board
- Task Guide
- Probing the Device Under Test
- Choosing the Sampling Mode
- To select transitional timing or store qualified
- Formatting Labels for Logic Analyzer Probes
- Setting Up Triggers and Running Measurements
- Displaying Captured Data
- Using Symbols
- Printing/Exporting Captured Data
- Cross-Triggering
- Solving Logic Analysis Problems
- Saving and Loading Logic Analyzer Configurations
- Reference
- The Sampling Tab
- The Format Tab
- Importing Netlist and ASCII Files
- The Trigger Tab
- The Symbols Tab
- Error Messages
- Must assign Pod 1 on the master card to specify actions for flags
- Branch expression is too complex
- Cannot specify range on label with clock bits that span pod pairs
- Counter value checked as an event, but no increment action specified
- Goto action specifies an undefined level
- Maximum of 32 Channels Per Label
- Hardware Initialization Failed
- Must assign another pod pair to specify actions for flags
- No more Edge/Glitch resources available for this pod pair
- No more Pattern resources available for this pod pair
- No Trigger action found in the trace specification
- Slow or Missing Clock
- Timer value checked as an event, but no start action specified
- Trigger function initialization failure
- Trigger inhibited during timing prestore
- Trigger Specification is too complex
- Waiting for Trigger
- Analyzer armed from another module contains no "Arm in from IMB" event
- Specifications and Characteristics
- Concepts
- Understanding Logic Analyzer Triggering
- Understanding State Mode Sampling Positions
- Getting Started
- Glossary
- Index
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Chapter 2: Task Guide
Formatting Labels for Logic Analyzer Probes
• LVCMOS 1.5v -- The threshold level is +0.75 volts.
• LVCMOS 1.8v -- The threshold level is +0.90 volts.
• LVCMOS 2.5v -- The threshold level is +1.25 volts.
• LVCMOS 3.3v -- The threshold level is +1.65 volts.
• CMOS 5.0v -- The threshold level is +2.50 volts.
• ECL -- The threshold level is -1.3 volts.
• LVPECL -- The threshold level is 2.00 volts.
3. If you don't want the change to apply to all pods, deselect the checked box
next to Apply settings to all pods.
4. Select the Close button.
User Defined
When User Defined is selected, the threshold level is selectable from -
6.0 volts to +6.0 volts.
NOTE: The logic analyzer requires a minimum voltage swing of 500 mV at the probe
tip to recognize changes in logic levels.
NOTE: The threshold voltage specified also applies to the pod's clock input.
To assign probe channels to labels
The logic analyzer lets you assign names (labels) to logic analyzer
channels so that it's easier to set up triggers and interpret the captured
data when displayed.
Typically, you give labels the names of the buses and signals in the
device under test that are are being probed.
1. In the Format tab, select a label button, and either:
• Choose the Rename command, enter the label name, and select the OK
button.