User's Manual
Table Of Contents
- Agilent Technologies 16750A/B Logic Analyzer
- Agilent Technologies 16750A/B Logic Analyzer
- Contents
- Getting Started
- Step 1. Connect the logic analyzer to the device under test
- Step 2. Choose the sampling mode
- Step 3. Format labels for the probed signals
- Step 4. Define the trigger condition
- Step 5. Run the measurement
- Step 6. Display the captured data
- For More Information...
- Example: Timing measurement on counter board
- Example: State measurement on counter board
- Task Guide
- Probing the Device Under Test
- Choosing the Sampling Mode
- To select transitional timing or store qualified
- Formatting Labels for Logic Analyzer Probes
- Setting Up Triggers and Running Measurements
- Displaying Captured Data
- Using Symbols
- Printing/Exporting Captured Data
- Cross-Triggering
- Solving Logic Analysis Problems
- Saving and Loading Logic Analyzer Configurations
- Reference
- The Sampling Tab
- The Format Tab
- Importing Netlist and ASCII Files
- The Trigger Tab
- The Symbols Tab
- Error Messages
- Must assign Pod 1 on the master card to specify actions for flags
- Branch expression is too complex
- Cannot specify range on label with clock bits that span pod pairs
- Counter value checked as an event, but no increment action specified
- Goto action specifies an undefined level
- Maximum of 32 Channels Per Label
- Hardware Initialization Failed
- Must assign another pod pair to specify actions for flags
- No more Edge/Glitch resources available for this pod pair
- No more Pattern resources available for this pod pair
- No Trigger action found in the trace specification
- Slow or Missing Clock
- Timer value checked as an event, but no start action specified
- Trigger function initialization failure
- Trigger inhibited during timing prestore
- Trigger Specification is too complex
- Waiting for Trigger
- Analyzer armed from another module contains no "Arm in from IMB" event
- Specifications and Characteristics
- Concepts
- Understanding Logic Analyzer Triggering
- Understanding State Mode Sampling Positions
- Getting Started
- Glossary
- Index

47
Chapter 2: Task Guide
To select transitional timing or store qualified
See Also “To change the sampling clock mode” on page 44
To automatically adjust sampling positions
When adjusting the state mode sampling position with eye finder, the
logic analyzer looks at signals from the device under test, figures out
the location of the data valid window in relation to the sampling clock,
and automatically sets the sampling position.
Because eye finder automatically runs on individual channels, it can
correct for the small delay effects caused by probe cables and circuit
board traces. This makes the logic analyzer's setup/hold window
smaller and lets you accurately capture data at higher clock speeds.
Eye finder requires:
• At least 500 transitions on each signal during its run. (You can use the
advanced eye finder settings to cause longer or shorter runs.)
• All devices which can drive each signal should contribute to the stimulus.
• All device under test operating modes relevant to the eventual logic
analysis measurement should contribute to the stimulus as well.
NOTE: Eye finder measurements and normal logic analyzer measurements cannot
run simultaneously.
To run eye finder
1. Probe the device under test by connecting the logic analyzer channels.
2. Select the state (synchronous sampling) mode (see “To select the state
mode” on page 44).
3. Format labels for those logic analyzer channels.
4. Make sure that the device under test and the logic analyzer have warmed
up to their normal operating temperatures.
5. In the Format tab, select the Setup/Hold button.
6. In the Sampling Positions dialog, select the Eye Finder option.
7. In the Eye Finder Setup tab, select the Use signals from Device Under
Test option.