User's Manual
Table Of Contents
- Agilent Technologies 16750A/B Logic Analyzer
- Agilent Technologies 16750A/B Logic Analyzer
- Contents
- Getting Started
- Step 1. Connect the logic analyzer to the device under test
- Step 2. Choose the sampling mode
- Step 3. Format labels for the probed signals
- Step 4. Define the trigger condition
- Step 5. Run the measurement
- Step 6. Display the captured data
- For More Information...
- Example: Timing measurement on counter board
- Example: State measurement on counter board
- Task Guide
- Probing the Device Under Test
- Choosing the Sampling Mode
- To select transitional timing or store qualified
- Formatting Labels for Logic Analyzer Probes
- Setting Up Triggers and Running Measurements
- Displaying Captured Data
- Using Symbols
- Printing/Exporting Captured Data
- Cross-Triggering
- Solving Logic Analysis Problems
- Saving and Loading Logic Analyzer Configurations
- Reference
- The Sampling Tab
- The Format Tab
- Importing Netlist and ASCII Files
- The Trigger Tab
- The Symbols Tab
- Error Messages
- Must assign Pod 1 on the master card to specify actions for flags
- Branch expression is too complex
- Cannot specify range on label with clock bits that span pod pairs
- Counter value checked as an event, but no increment action specified
- Goto action specifies an undefined level
- Maximum of 32 Channels Per Label
- Hardware Initialization Failed
- Must assign another pod pair to specify actions for flags
- No more Edge/Glitch resources available for this pod pair
- No more Pattern resources available for this pod pair
- No Trigger action found in the trace specification
- Slow or Missing Clock
- Timer value checked as an event, but no start action specified
- Trigger function initialization failure
- Trigger inhibited during timing prestore
- Trigger Specification is too complex
- Waiting for Trigger
- Analyzer armed from another module contains no "Arm in from IMB" event
- Specifications and Characteristics
- Concepts
- Understanding Logic Analyzer Triggering
- Understanding State Mode Sampling Positions
- Getting Started
- Glossary
- Index

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Chapter 2: Task Guide
To select transitional timing or store qualified
To set up the master/slave sampling clock mode
1. In the Sampling tab, with State Mode selected, select the Master/Slave
mode in the Clock Setup area.
2. In the Format tab, select Slave Clock for each pod that should use the
slave clock, and select Master Clk for each pod that should use the master
clock.
To set up the demultiplex sampling clock mode
1. In the Sampling tab, with State Mode selected, select the Demultiplex
mode in the Clock Setup area.
2. In the Format tab, select Demultiplex for the pod pair that should use this
mode.
To set up the sampling clock
1. In the Sampling tab, with the State Mode selected, make sure the
Advanced Clocking box is unchecked.
2. For each clock input signal that will be used:
a. Select the pod's Master or Slave button (under the activity indicator).
b. If the signal edge will specify when to sample, choose Rising Edge,
Falling Edge, or Both Edges.
c. If the signal level will enable the sampling clock, choose Qualifier -
High or Qualifier - Low.
3. Make sure all unused clock inputs are turned Off.
To set up using advanced clocking
1. In the Sampling tab, with the State Mode selected, select the Advanced
Clocking check box.
2. Select the Master Clock button. In the Master clock dialog, select the
appropriate options for setting up the master clock.
3. If you have chosen the Master/Slave or Demultiplex clock mode, select the
Slave Clock button. In the Slave clock dialog, select the appropriate
options for setting up the slave clock.