User's Manual
Table Of Contents
- Agilent Technologies 16750A/B Logic Analyzer
- Agilent Technologies 16750A/B Logic Analyzer
- Contents
- Getting Started
- Step 1. Connect the logic analyzer to the device under test
- Step 2. Choose the sampling mode
- Step 3. Format labels for the probed signals
- Step 4. Define the trigger condition
- Step 5. Run the measurement
- Step 6. Display the captured data
- For More Information...
- Example: Timing measurement on counter board
- Example: State measurement on counter board
- Task Guide
- Probing the Device Under Test
- Choosing the Sampling Mode
- To select transitional timing or store qualified
- Formatting Labels for Logic Analyzer Probes
- Setting Up Triggers and Running Measurements
- Displaying Captured Data
- Using Symbols
- Printing/Exporting Captured Data
- Cross-Triggering
- Solving Logic Analysis Problems
- Saving and Loading Logic Analyzer Configurations
- Reference
- The Sampling Tab
- The Format Tab
- Importing Netlist and ASCII Files
- The Trigger Tab
- The Symbols Tab
- Error Messages
- Must assign Pod 1 on the master card to specify actions for flags
- Branch expression is too complex
- Cannot specify range on label with clock bits that span pod pairs
- Counter value checked as an event, but no increment action specified
- Goto action specifies an undefined level
- Maximum of 32 Channels Per Label
- Hardware Initialization Failed
- Must assign another pod pair to specify actions for flags
- No more Edge/Glitch resources available for this pod pair
- No more Pattern resources available for this pod pair
- No Trigger action found in the trace specification
- Slow or Missing Clock
- Timer value checked as an event, but no start action specified
- Trigger function initialization failure
- Trigger inhibited during timing prestore
- Trigger Specification is too complex
- Waiting for Trigger
- Analyzer armed from another module contains no "Arm in from IMB" event
- Specifications and Characteristics
- Concepts
- Understanding Logic Analyzer Triggering
- Understanding State Mode Sampling Positions
- Getting Started
- Glossary
- Index

44
Chapter 2: Task Guide
To select transitional timing or store qualified
To select the state mode
1. Open the logic analyzer Setup window.
2. Select the Sampling tab.
3. Choose the State Mode option.
You can also select the state sampling mode in the “Pod Assignment
Dialog” on page 130.
To select the 200 MHz/400 MHz state speed configuration
1. In the Sampling tab, with State Mode selected, select the state analyzer
configuration. You can choose between:
• 200 MHz / 4M State
In this configuration, all pods are available.
Memory depth is 4M samples per channel. If time or state count is
turned on in Trigger Settings, the total memory is split between data
acquisition storage and time or state count storage. To maintain the full
memory depth of 4M samples per channel, leave one pod pair
unassigned. (To unassign a pod pair, select the Pod Assignment button
in the Format tab, then drag a pod pair to unassigned.)
State clock speed matches your device under test's clock, up to 200
MHz.
• 400 MHz / 4M State
This configuration is similar to the 200 MHz State mode, except
clocking is restricted to the J clock on Pod 1 of the master card of the
module, and triggering is restricted to two trigger functions.
NOTE: When Store Qualification is performed in the 400 MHz State mode, there may
be the case where data occupying memory is further disqualified. As a result,
you may see a non-contiguous listing of states as well as a reduction of usable
memory.
To change the sampling clock mode
Normally, in the Master only sampling clock mode, there is one
sampling clock signal. When a clock edge occurs, data is captured and