User's Manual
Table Of Contents
- Agilent Technologies 16750A/B Logic Analyzer
- Agilent Technologies 16750A/B Logic Analyzer
- Contents
- Getting Started
- Step 1. Connect the logic analyzer to the device under test
- Step 2. Choose the sampling mode
- Step 3. Format labels for the probed signals
- Step 4. Define the trigger condition
- Step 5. Run the measurement
- Step 6. Display the captured data
- For More Information...
- Example: Timing measurement on counter board
- Example: State measurement on counter board
- Task Guide
- Probing the Device Under Test
- Choosing the Sampling Mode
- To select transitional timing or store qualified
- Formatting Labels for Logic Analyzer Probes
- Setting Up Triggers and Running Measurements
- Displaying Captured Data
- Using Symbols
- Printing/Exporting Captured Data
- Cross-Triggering
- Solving Logic Analysis Problems
- Saving and Loading Logic Analyzer Configurations
- Reference
- The Sampling Tab
- The Format Tab
- Importing Netlist and ASCII Files
- The Trigger Tab
- The Symbols Tab
- Error Messages
- Must assign Pod 1 on the master card to specify actions for flags
- Branch expression is too complex
- Cannot specify range on label with clock bits that span pod pairs
- Counter value checked as an event, but no increment action specified
- Goto action specifies an undefined level
- Maximum of 32 Channels Per Label
- Hardware Initialization Failed
- Must assign another pod pair to specify actions for flags
- No more Edge/Glitch resources available for this pod pair
- No more Pattern resources available for this pod pair
- No Trigger action found in the trace specification
- Slow or Missing Clock
- Timer value checked as an event, but no start action specified
- Trigger function initialization failure
- Trigger inhibited during timing prestore
- Trigger Specification is too complex
- Waiting for Trigger
- Analyzer armed from another module contains no "Arm in from IMB" event
- Specifications and Characteristics
- Concepts
- Understanding Logic Analyzer Triggering
- Understanding State Mode Sampling Positions
- Getting Started
- Glossary
- Index

217
Glossary
machine because the master card is
in slot C of the mainframe. The other
cards of the module are called
expansion cards.
menu bar The menu bar is located
at the top of all windows. Use it to
select File operations, tool or system
Options, and tool or system level
Help.
message bar The message bar
displays mouse button functions for
the window area or field directly
beneath the mouse cursor. Use the
mouse and message bar together to
prompt yourself to functions and
shortcuts.
module/probe interconnect cable
The module/probe interconnect cable
connects an E5901B emulation
module to an E5900B emulation
probe. It provides power and a serial
connection. A LAN connection is also
required to use the emulation probe.
module An instrument that uses a
single timebase in its operation.
Modules can have from one to five
cards functioning as a single
instrument. When a module has more
than one card, system window will
show the instrument icon in the slot
of the master card.
monitor When using the Emulation
Control Interface, running the
monitor means the processor is in
debug mode (that is, executing the
debug exception) instead of
executing the user program.
panning The action of moving the
waveform along the timebase by
varying the delay value in the Delay
field. This action allows you to
control the portion of acquisition
memory that will be displayed on the
screen.
pattern mode In an oscilloscope,
the trigger mode that allows you to
set the oscilloscope to trigger on a
specified combination of input signal
levels.
pattern terms Logic analyzer
resources that represent single states
to be found on labeled sets of bits; for
example, an address on the address
bus or a status on the status lines.
period (.) See edge terms, glitch,
labels, and don't care.
pod pair A group of two pods
containing 16 channels each, used to
physically connect data and clock
signals from the unit under test to the
analyzer. Pods are assigned by pairs
in the analyzer interface. The number
of pod pairs available is determined